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74HC175

Quad D-type flip-flop with reset; positive-edge trigger

NXP Semiconductors. 

NXP Semiconductors

74HC175; 74HCT175

Quad D-type flip-flop with reset; positive-edge trigger

10. Dynamic characteristics

Table 7. Dynamic characteristics

GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 11

Symbol Parameter

Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max

Min

Max

74HC175

tpd

propagation

CP to Qn, Qn;

[1]

delay

see Figure 8

VCC = 2.0 V

- 55 175 -

VCC = 4.5 V

- 20 35 -

VCC = 5 V; CL = 15 pF

- 17 - -

VCC = 6.0 V

- 16 30 -

tPHL

HIGH to LOW MR to Qn, Qn;

propagation

see Figure 10

delay

VCC = 2.0 V

- 50 150 -

VCC = 4.5 V

- 18 30 -

VCC = 5 V; CL = 15 pF

- 15 - -

VCC = 6.0 V

- 14 26 -

tt

transition time Qn output; see Figure 8 [2]

VCC = 2.0 V

- 19 75 -

VCC = 4.5 V

- 7 15 -

VCC = 6.0 V

- 6 13 -

tW

pulse width

CP input HIGH or LOW;

see Figure 8

220 -

44

-

-

-

37

-

190 -

38

-

-

-

33

-

95

-

19

-

16

-

265

ns

53

ns

-

ns

45

ns

225

ns

45

ns

-

ns

38

ns

110

ns

22

ns

19

ns

VCC = 2.0 V

VCC = 4.5 V

VCC = 6.0 V

MR input LOW;

see Figure 10

80 22 - 100 -

120

-

ns

16 8 - 20

-

24

-

ns

14 6 - 17

-

20

-

ns

VCC = 2.0 V

80 19 - 100 -

120

-

ns

VCC = 4.5 V

16 7 - 20

-

24

-

ns

VCC = 6.0 V

14 6 - 17

-

20

-

ns

trec

recovery time MR to CP; see Figure 10

VCC = 2.0 V

5 33 - 5

-

5

-

ns

VCC = 4.5 V

5 12 - 5

-

5

-

ns

VCC = 6.0 V

5 10 - 5

-

5

-

ns

tsu

set-up time

Dn to CP; see Figure 8

VCC = 2.0 V

80 3 - 100 -

120

-

ns

VCC = 4.5 V

16 1 - 20

-

24

-

ns

VCC = 6.0 V

14 1 - 17

-

20

-

ns

74HC_HCT175

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 8 April 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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