MCP79521T 데이터 시트보기 (PDF) - Microchip Technology

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MCP79521T

2Kb EE 64B SRAM WD TED ID

Microchip Technology 

MCP795W1X/MCP795W2X

3.3 Write Enable (EEWREN) and Write

Disable (EEWRDI)

The MCP795WXX contains a write enable latch.

This latch must be set before any EEWRITE,

SRWRITE and IDWRITE operation will be completed

internally. The EEWREN instruction will set the latch, and

the EEWRDI will reset the latch.

The following is a list of conditions under which the

write enable latch will be reset:

• Power-up

• EEWRDI instruction successfully executed

• SRWRITE instruction successfully executed

• EEWRITE instruction successfully executed

• IDWRITE instruction successfully executed

FIGURE 3-4:

WRITE ENABLE SEQUENCE (EEWREN)

CS

SCK

01234567

SI

00000110

High-Impedance

SO

FIGURE 3-5:

WRITE DISABLE SEQUENCE (EEWRDI)

CS

SCK

01234567

SI

0 0 0 0 0 1 00

High-Impedance

SO

DS22280C-page 10

Preliminary

 2011-2012 Microchip Technology Inc.

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