74HCT4046AD 데이터 시트보기 (PDF) - NXP Semiconductors.

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74HCT4046AD

Phase-locked loop with VCO

NXP Semiconductors. 

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

PC1 is fed to the VCO input via the low-pass filter and provided at the demodulator output at pin

DEM_OUT (VDEM_OUT). The average output voltage from PC1 is the result of the phase differences

of signals (SIG_IN) and the comparator input (COMP_IN). These phase differences are shown in

Fig. 7. The average of VDEM_OUT is equal to 0.5VCC when no signal or noise is present at SIG_IN.

Using this input, the VCO oscillates at the center frequency (f0). Typical waveforms for the PC1

loop locked at f0 are shown in Fig. 8.

The frequency capture range (2fc) is defined as the frequency range of input signals on which the

PLL locks when it was initially out-of-lock. The frequency lock range (2fL) is the frequency range of

the input signals on which the loop stays locked when it was initially in lock. The capture range is

smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass filter characteristics and can be made as

large as the lock range. This configuration remains locked even with very noisy input signals.

Typical behavior of this type of phase comparator is that it can lock to input frequencies close to the

harmonics of the VCO center frequency.

VCC

VDEM_OUT

(V)

1/2 VCC

0

0

π/2

ØDEM_OUT(rad)

π

aaa-020206

Fig. 7. Phase comparator 1; average output voltage as a function of input phase

difference

SIG_IN

COMP_IN

VCO_OUT

PC1_OUT

VCO_IN

VCC

GND

aaa-020207

Fig. 8. Typical waveforms for PLL using phase comparator 1; loop-locked at f0

74HC_HCT4046A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 6 August 2019

© Nexperia B.V. 2019. All rights reserved

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