T14M1024-10J 데이터 시트보기 (PDF) - Taiwan Memory Technology
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T14M1024-10J Datasheet PDF : 10 Pages
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tm TE
CH
SRAM
T14M1024A
128K X 8 HIGH SPEED
CMOS STATIC RAM
FEATURES
• Fast Address Access Times : 10/12/15ns
• Single 5V +10% power supply
• Low Power Consumption : 110/105/100mA
• TTL I/O compatible
• 2.0V data retention mode
• Automatic power-down when deselected
• Available packages :
32-pin 300 mil SOJ & 32-pin TSOP-I
• Industry Standard Pin Assignment
PIN CONFIGURATION
NC 1
A10 2
A9
3
A8
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
Vss 16
SOJ
32 Vcc
31 A11
30 CE2
29 WE
28 A12
27 A13
26 A14
25 A15
24 OE
23 A16
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A15
1
A14
2
A13
3
A12
4
WE
5
CE2
6
A11
7
VCC
8
NC
9
A10
10
A9
11
A8
12
A7
13
A6
14
A5
15
A4
16
TSOP-I
32
OE
31
A16
30
CE1
29
I/O7
28
I/O6
27
I/O5
26
I/O4
25
I/O3
24
VSS
23
I/O2
22
I/O1
21
I/O0
20
A0
19
A1
18
A2
17
A3
GENERAL DESCRIPTION
The T14M1024A is a one-megabit density, fast
static random access memory organized as 131,072
words by 8 bits. It is designed for use in high
performance memory applications such as main
memory storage and high speed communication
buffers. Fabricated using high performance CMOS
technology, access times down to 10ns are achieved.
Memory expansion by banking is easily
accomplished using the chip enable pins CE1 and
CE2. This device is packaged in a standard 32-pin
300 mil SOJ and 32-pin TSOP-I.
BLOCK DIAGRAM
CE1
CE2
Vcc
Vss
A0
...
DECODER
.
A16
WE
OE
CORE
ARRAY
DATA I/O
I/O0
..
.
I/O7
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O0 - I/O7
CE1,CE2
WE
OE
Vcc
Vss
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable
Output Enable
Power Supply
Ground
PART NUMBER EXAMPLES
PACKAGE SPEED
T14M1024A-10J SOJ 300mil
10ns
T14M1024A-10P TSOP-I 8x13.4mm 10ns
T14M1024A-10H TSOP-I 8x20mm 10ns
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: SEP. 2002
Revision:E
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