LE82Q35SLJA7 데이터 시트보기 (PDF) - Intel
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LE82Q35SLJA7 Datasheet PDF : 438 Pages
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3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
PCI Memory Address Range (TOLUD – 4GB) .............................................61
3.3.1
3.3.2
3.3.3
3.3.4
APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................63
HSEG (FEDA_0000h–FEDB_FFFFh).............................................63
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................. 63
High BIOS Area.......................................................................63
Main Memory Address Space (4 GB to TOUUD) .........................................64
3.4.1
3.4.2
Memory Re-claim Background ...................................................65
Memory Reclaiming .................................................................65
PCI Express* Configuration Address Space...............................................65
PCI Express* Graphics Attach (PEG)........................................................66
Graphics Memory Address Ranges (Intel® 82Q35, 82Q33, and 82G33
(G)MCH Only) ......................................................................................67
System Management Mode (SMM) ..........................................................67
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
SMM Space Definition ..............................................................68
SMM Space Restrictions............................................................68
SMM Space Combinations .........................................................69
SMM Control Combinations .......................................................69
SMM Space Decode and Transaction Handling..............................69
Processor WB Transaction to an Enabled SMM Address Space ........69
SMM Access through GTT TLB (Intel® 82Q35, 82Q33, 82G33
GMCH Only) ...........................................................................70
Memory Shadowing ..............................................................................70
I/O Address Space................................................................................70
3.10.1 PCI Express* I/O Address Mapping ............................................71
(G)MCH Decode Rules and Cross-Bridge Address Mapping ..........................72
3.11.1 Legacy VGA and I/O Range Decode Rules ...................................72
4
(G)MCH Register Description ............................................................................73
4.1 Register Terminology ............................................................................74
4.2 Configuration Process and Registers ........................................................76
4.2.1 Platform Configuration Structure ...............................................76
4.3 Configuration Mechanisms .....................................................................77
4.3.1
4.3.2
Standard PCI Configuration Mechanism ......................................77
PCI Express* Enhanced Configuration Mechanism ........................77
4.4 Routing Configuration Accesses ..............................................................79
4.4.1
4.4.2
Internal Device Configuration Accesses.......................................80
Bridge Related Configuration Accesses........................................80
4.4.2.1 PCI Express* Configuration Accesses ........................... 80
4.4.2.2 DMI Configuration Accesses .......................................81
4.5 I/O Mapped Registers ...........................................................................81
4.5.1
4.5.2
CONFIG_ADDRESS—Configuration Address Register ..................... 81
CONFIG_DATA—Configuration Data Register ............................... 83
5
DRAM Controller Registers (D0:F0)....................................................................85
5.1 DRAM Controller (D0:F0).......................................................................85
5.1.1 VID—Vendor Identification........................................................87
5.1.2 DID—Device Identification ........................................................87
5.1.3 PCICMD—PCI Command ...........................................................88
5.1.4 PCISTS—PCI Status .................................................................89
5.1.5 RID—Revision Identification ......................................................90
5.1.6 CC—Class Code.......................................................................91
5.1.7
5.1.8
MLT—Master Latency Timer ......................................................91
HDR—Header Type ..................................................................92
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Datasheet
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