9534 데이터 시트보기 (PDF) - NXP Semiconductors.

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9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

NXP Semiconductors. 

NXP Semiconductors

PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

data from

shift register

data from

shift register

write configuration

pulse

configuration

register

DQ

FF

CK Q

write pulse

read pulse

data from

shift register

write polarity

pulse

DQ

FF

CK

output port

register

Q1

Q2

input port

register

DQ

FF

CK

polarity inversion

register

DQ

FF

CK

Remark: At power-on reset, all registers return to default values.

Fig 6. Simplified schematic of IO0 to IO7

6.5 Device address

output port

register data

VDD

IO0 to IO7

VSS

input port

register data

to INT

polarity inversion

register data

002aac470

slave address

0 1 0 0 A2 A1 A0 R/W

fixed

Fig 7. PCA9534 device address

hardware

selectable

002aac471

6.6 Bus transactions

Data is transmitted to the PCA9534 registers using the Write mode as shown in Figure 8

and Figure 9. Data is read from the PCA9534 registers using the Read mode as shown in

Figure 10 and Figure 11. These devices do not implement an auto-increment function, so

once a command byte has been sent, the register which was addressed will continue to

be accessed by reads until a new command byte has been sent.

PCA9534

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 7 November 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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