ADV7625 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

ADV7625

Video ICs 5:2 Crosspoint TRX audio I/O OSD 16bTTL

Analog Devices 

ADV7625

Data Sheet

Parameter

Symbol Test Conditions/Comments Min

Typ

Max

Unit

APx_OUT Data Transition Time

t49

Start of invalid data to falling

APx_OUT_SCLK edge

10

ns

APx_OUT Data Transition Time

t50

Falling APx_OUT_SCLK edge

to end of invalid data

10

ns

AUDIO OUTPUT PORTS, DSD OUTPUT

APx_OUT_SCLK High Time

t51

45

55

% duty

cycle

APx_OUT_SCLK Low Time

45

55

% duty

cycle

APx_OUT DSD Data Transition Time t52

Start of invalid data to falling

APx_OUT_SCLK edge

10

ns

APx_OUT DSD Data Transition Time t53

Falling APx_OUT_SCLK edge

to end of invalid data

10

ns

1 xCL refers to SCL, DDC_SCL_RXA, DDC_SCL_RXB, DDC_SCL_RXC, DDC_SCL_RXD, and DDC_SCL_RXE.

2 xDA refers to SDA, DDC_SDA_RXA, DDC_SDA_RXB, DDC_SDA_RXC, DDC_SDA_RXD, and DDC_SDA_RXE.

3 SPI Mode 0 only.

4 All serial port measurements are for CPHA = 0, CPOL = 0 (clock is low in idle state; negative edge of clock is used to transmit data and positive edge is used to sample data).

5 Measurements guaranteed by design only.

Timing Diagrams

t3

xDA

t5

t3

t6

t1

xCL

t2

t7

t4

t8

Figure 3. I2C Timing

t9

t10

EP_CS

EP_SCLK

t13

t11

t12

EP_MOSI

EP_MISO

INSTRUCTION

(0x0B)

24-BIT

ADDRESS

DUMMY BYTE

23 22 21 ... 3 2 1 0 7 6 5 4 3 2 1 0

DATA OUT 1

DATA OUT 2

7 654321076543210

Figure 4. Detailed SPI Master Timing Diagram (SPI Mode 0, CPOL = CPHA = 0)

EP_SCLK

EP_MOSI

EP_CS

EP_MISO

(FALLING EDGE CAPTURE)

EP_MISO

(RISING EDGE CAPTURE)

t14

t15

t16

t17

t17

t18

t18

Figure 5. SPI Master Mode Timing (SPI Mode 0)

Rev. 0 | Page 8 of 24

Share Link: