24C128 데이터 시트보기 (PDF) - ON Semiconductor
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24C128 Datasheet PDF : 16 Pages
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CAT24C128
BUS ACTIVITY: S
T
A
MASTER R
T
SLAVE
ADDRESS
ADDRESS
BYTE
a13−a8
ADDRESS
BYTE
a7−a0
DATA
BYTE
n
S
**
A
SLAVE
C
K
* = Don’t Care Bit
P v 63
A
A
A
C
C
C
K
K
K
Figure 8. Page Write Sequence
DATA
BYTE
n+1
AA
CC
KK
DATA
S
BYTE
T
n+P
O
P
P
A
C
K
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
8
SCL
SDA
a7
a0
d7
d0
tSU:WP
WP
tHD:WP
Figure 9. WP Timing
Read Operations
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24C128 will interpret this as a request for data
residing at the current byte address in memory. The
CAT24C128 will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24C128
returns to Standby mode.
Selective Read
To read data residing at a specific location, the internal
address counter must first be initialized as described under
Byte Write. If rather than following up the two address bytes
with data, the Master instead follows up with an Immediate
Read sequence, then the CAT24C128 will use the 14 active
address bits to initialize the internal address counter and will
shift out data residing at the corresponding location. If the
Master does not acknowledge the data (NoACK) and then
follows up with a STOP condition (Figure 11), the
CAT24C128 returns to Standby mode.
Sequential Read
If during a Read session the Master acknowledges the 1st
data byte, then the CAT24C128 will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wrap−around at end of memory (rather than end of page).
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