RK3026 데이터 시트보기 (PDF) - Rockchips

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RK3026

High Performance and Low-power Processor for Digital Media Application

Rockchips 

chapter 1 Introduction

BRIEF

RK3026

1.1 Overview

RK3026 is a low power, high performance processor solution for tablet, and other

digital multimedia applications, and integrates Dual-core Cortex-A9 with separately Neon

and FPU coprocessor ,and also with 256KB L2 Cache.

Many embedded powerful hardware engines provide optimized performance for

high-end application. RK3026 supports almost full-format video decoder by 1080p@60fps,

also support H.264/MVC/VP8 encoder by 1080p@30fps, high-quality JPEG

encoder/decoder and special image preprocessor and postprocessor .

Embedded 3D GPU makes RK3026 completely compatible with OpenGL ES1.1 and 2.0,

OpenVG 1.1 etc. Special 2D hardware engine with MMU will maximize display performance.

RK3026 has high-performance external memory interface(DDR3/LVDDR3) capable of

sustaining demanding memory bandwidths, also provides a complete set of peripheral

interface to support very flexible applications as follows :

 Support 8bits async Nand Flash, sync Toggle Nand Flash, LBA Nand Flash and sync

ONFI Nand Flash, 4 banks,all embedded up to 60bits hardware ECC

 2 ranks, 1GB Memory space, 16bits DDR3-1066, LVDDR3-1066

 Support 8bits eMMC

 One-channels SD/MMC interface to support 4bits MMC4.41, SD3.0 or SDIO3.0

 4-layers TFT LCD Controller, 24bits data, 1920x1080 maximum display size

 18/24 bits LVDS output, and comply with the Standard TIA/EIA-644-A LVDS

 One-channel, 8bits CCIR656 interface and 8bits Raw data interface

 One I2S/PCM interface

 One USB OTG 2.0 and one USB Host2.0 interface

 3x I2C, 1xUART with hardware flow-control , 1x SPI , 2x PWM

 Audio Codec with Mono Microphone interface

1.2 Features

1.2.1 MicroProcessor

 Dual-core ARM Cortex-A9 processor is a high-performance, low-power, cached

application processor

 Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced

SIMD (single instruction, multiple data) support for accelerated media and signal

processing computation

 Superscalar, variable length, out-of-order pipeline with dynamic branch prediction,

8-stage pipeline

 Include VFPv3 hardware to support single and double-precision add, subtract, divide,

multiply and accumulate, and square root operations

 Integrated timer and watchdog timer in CPU

 Integrated 32KB L1 instruction cache , 32KB L1 data cache, 4-way set associative

 256KB unified L2 Cache

 coresight debug solution

 Invasive debug

 One isolated voltage domain to support DVFS

 Maximum frequency can be up to 1.0GHz@1.1V, 25°C

High Performance and Low-power Processor for Digital Media Application

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