RK3026 데이터 시트보기 (PDF) - Rockchips

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RK3026

High Performance and Low-power Processor for Digital Media Application

Rockchips 

BRIEF

RK3026

 Embedded clock frequency division control to provide programmable baud rate

 Support block size from 1 to 65535Bytes

 8bits data bus width

 SD/MMC Interface

 Compatible with SD2.0, MMC ver4.41

 Support combined single FIFO(32x32bits) for both transmit and receive operations

 Support FIFO over-run and under-run prevention by stopping card clock

automatically

 Support CRC generation and error detection

 Embedded clock frequency division control to provide programmable baud rate

 Support block size from 1 to 65535Bytes

Data bus width is 4bits

1.2.5 System Component

 CRU (clock & reset unit)

 Support clock gating control for individual components inside RK3026

 Support global soft-reset control for whole SOC, also individual soft-reset for every

components

 Support flexible clock solution, including clock source, clock mux, clock frequency

division

 One oscillator with 24MHz clock and 4 embedded PLLs

 Timer

 On-chip 64bits Timers with interrupt-based operation

 Provide two operation modes: free-running and user-defined count

 Support timer work state checkable

 24MHz/PCLK clock input for operating domain, and PCLK input for bus interface

domain.

 PWM

 On-chip PWMs with interrupt-based operation

 Programmable 4-bit pre-scalar from apb bus clock

 Embedded 32-bit timer/counter facility

 Support single-run or continuous-run PWM mode

 Provides reference mode and output various duty-cycle waveform

 WatchDog

 32 bits watchdog counter width

 Counter clock is from apb bus clock

 Counter counts down from a preset value to 0 to indicate the occurrence of a

timeout

 WDT can perform two types of operations when timeout occurs:

 Generate a system reset

 First generate an interrupt and if this is not cleared by the service routine by

the time a second timeout occurs then generate a system reset

 Programmable reset pulse length

 Totally 16 defined-ranges of main timeout period

 Bus Architecture

 QoS function is supported to improve the utility of bus bandwidth

 Interrupt Controller

 Support 3 PPI interrupt source and 96 SPI interrupt sources input from different

components inside RK3026

 Support 16 softwre-triggered interrupts

 Input interrupt level is fixed , only high-level sensitive

 Two interrupt output (nFIQ and nIRQ) to per Cortex-A9, both are low-level

High Performance and Low-power Processor for Digital Media Application

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