PTN3392 데이터 시트보기 (PDF) - NXP Semiconductors.
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PTN3392 Datasheet PDF : 32 Pages
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NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
Table 4. PTN3392 specific DPCD registers …continued
DPCD
Description
register [1]
Power-on Read/write
Reset value over AUX CH
Link Configuration Field
00109h
I2C-bus speed control/status bit map. Bit values in this register are assigned to S2 setting
I2C-bus speeds as follows:
read/write
Bits 7:0
0000 0001b = 1 kbit/s; supported by PTN3392
0000 0010b = 3 kbit/s; supported by PTN3392
0000 0100b = 10 kbit/s; supported by PTN3392
0000 1000b = 100 kbit/s; supported by PTN3392
0001 0000b = 400 kbit/s; not supported by PTN3392
0010 0000b = 1 Mbit/s; not supported by PTN3392
0100 0000b = reserved
1000 0000b = 50 kbit/s; supported by PTN3392BS/F3
1000 0000b = reserved in PTN3392BS/F1, PTN3392BS/F2
Default value: 1000 0000b (50 kbit/s) for PTN3392BS/F3
Default value: 0000 1000b (100 kbit/s) for PTN3392BS/F1, PTN3392BS/F2
See also behavior of pin S2 in Table 3.
Automated testing sub-field (optional)
00218h to Not supported.
0027Fh
Branch device-specific field
00500h
BRANCH_IEEE_OUI 7:0
00h
read only
Branch vendor 24-bit IEEE OUI.
NXP OUI = 00
00501h
BRANCH_IEEE_OUI 15:8
60h
read only
NXP OUI = 60
00502h
BRANCH_IEEE_OUI 23:16
37h
read only
NXP OUI = 37
00503h
ID string = 3392N2
33h
read only
00504h
33h
read only
00505h
39h
read only
00506h
32h
read only
00507h
4Eh
read only
00508h
32h
read only
00509h
Hardware revision level v1.2
12h
read only
0050Ah, Major revision level (example: v1.38),
01h,
read only
0050Bh
Minor revision level (example: v1.38)
26h
0050Ch to RESERVED
005FFh
read only
[1] Byte fields that are not explicitly listed are by definition reserved (‘RES’) and their default value is 0h.
PTN3392
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 5 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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