S34ML01G200BFI000(2012) 데이터 시트보기 (PDF) - Spansion Inc.
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S34ML01G200BFI000 Datasheet PDF : 68 Pages
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Data Sheet (Advance Information)
1. General Description
The Spansion S34ML01G2, S34ML02G2, and S34ML04G2 series is offered in 3.3 VCC and VCCQ power
supply, and with x8 I/O interface. Its NAND cell provides the most cost-effective solution for the solid state
mass storage market. The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. The page size is (2048 + spare) bytes.
To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the
NAND flash memory device by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache
reading, the devices load the data in a cache register while the previous data is transferred to the I/O buffers
to be read.
Like all other 2 kB-page NAND flash devices, a program operation typically writes to the page in 300 µs and
an erase operation can typically be performed in 3 ms (S34ML01G2) on a 128-kB block. In addition, thanks to
multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at
a time (again, one per plane). The multiplane architecture allows program time to be reduced by 40% and
erase time to be reduced by 50%.
In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as
the ports for command and address input as well as data input/output. This interface allows a reduced pin
count and easy migration towards different densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control
pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse
repetition, where required, and internal verification and margining of data. A WP# pin is available to provide
hardware protection against program and erase operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if
the program/erase/read controller is currently active. The use of an open-drain output allows the Ready/Busy
pins from several memories to connect to a single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program
operation fails the data can be directly programmed in another page inside the same array section without the
time consuming serial data insertion phase. The Copy Back operation automatically executes embedded
error detection operation: 4-bit error out of every 528-bytes can be detected. With this feature it is no longer
necessary to use an external mechanism to detect Copy Back operation errors.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane
cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by
programing data using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page
Reprogram re-programs one page. Normally, this operation is performed after a failed Page Program
operation. Similarly, the Multiplane Page Reprogram re-programs two pages in parallel, one per plane. The
first page must be in the first plane while the second page must be in the second plane. The Multiplane Page
Reprogram operation is performed after a failed Multiplane Page Program operation. The Page Reprogram
and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted
during re-program operations.
The devices are available in the TSOP48 (12 x 20 mm) package and come with the following security
features:
OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be
stored permanently.
Serial number (unique identifier), which allows the devices to be uniquely identified.
Read ID2 extension.
These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described
in the data sheet. For more details about them, contact your nearest Spansion sales office.
August 3, 2012 S34ML01G2_04G2_01
Spansion® SLC NAND Flash Memory for Embedded
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