RT8868A 데이터 시트보기 (PDF) - Richtek Technology
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RT8868A Datasheet PDF : 21 Pages
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RT8868A
VIN
5VCC
OCP Comparator
HS
PWM
Controller
ILX
LX_NB DCRNB
LS
RX_NB CX_NB
PSOC2P
Latch
EN
PSIA Control
(1) 5VCC for (4 phase to 2 phase)
(2) 3.3V for (4 phase to 1 phase)
VDDIO
PS
1.6V
1/4IIMAX_NB
1/8IX_NB
+
+
48
GM
-
-
IIMAX_NB
RCSN_NB
IX_NB
VIMAX_NB
RIMAX_NB
RT8868A NB section
Figure 13. Over Current Protection for NB Section
NB Section Over Voltage Protection (OVP)
The over voltage protection monitors the output voltage
via the FB_NB pin. Once VFB_NB exceeds 1.8V, OVP is
triggered and latched for NB section. The RT8868A will
try to turn on low side MOSFET and turn off high side
MOSFET to protect NB.
Power Saving Indicator (PSI)
This is an active low flag that can be set by the CPU to
allow the regulator to enter Power-Saving mode to
maximize the system efficiency when in light-load
conditions. The status of the flag is communicated to the
controller through either the SVI bus or PS pin. The
RT8868A monitors the PS pin to define the action
performed by the controller when PSI is asserted.
According to Figure 14, by programming different voltage
on PS pin, this configures the controller to operate in one
or two-phase condition when PSI is asserted. By pulling
up PS pin to 3.3V through a resistor, the controller
operates in only one-phase configuration. If the 3.3V is
changed to 5V, the RT8868A operates in two-phase
configuration. When PSI is de-asserted, the controller will
return to the original configuration. The PSI strategy is
summarized as shown in Table 5.
PSI
(From I2C)
PSI
(Active Low)
Figure 14. Power-Saving-Mode Circuit
Table 5. PSI Strategy
PS pin
Pull-Up to 3.3V
Pull-Up to 5V
PSI Strategy
Phase number is set to 1 while
PSI is asserted.
Phase number is set to 2 while
PSI is asserted.
Non-overlap Control of MOSFET Driver
To prevent the overlap of the gate drives during the UGATE
pull low and the LGATE pull high, the non-overlap circuit
monitors the voltages at the PHASE node and high side
gate drive (UGATE-PHASE). When the PWM input signal
goes low, UGATE begins to pull low (after propagation
delay). Before LGATE can pull high, the non-overlap
protection circuit ensures that the monitored voltages have
gone below 1.1V. Once the monitored voltages fall below
1.1V, LGATE begins to turn high. By waiting for the
voltages of the PHASE pin and high side gate drive to fall
below 1.1V, the non-overlap protection circuit ensures that
UGATE is low before LGATE pulls high.
Also to prevent the overlap of the gate drives during LGATE
pull low and UGATE pull high, the non-overlap circuit
monitors the LGATE voltage. When LGATE go below 1.1V,
UGATE goes high after propagation delay.
Layout Considerations
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The high power
switching power stage requires particular attention. Follow
these guidelines for optimum PCB layout.
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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