RT8868A 데이터 시트보기 (PDF) - Richtek Technology
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RT8868A Datasheet PDF : 21 Pages
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RT8868A
Place the power components first, including power
MOSFETs, input and output capacitors, and inductors. It
is important to have a symmetrical layout for each power
train, preferably with the controller located equidistant from
each. Symmetrical layout allows heat to be dissipated
equally across all power trains. Great attention should be
paid for routing the UGATE, LGATE, and PHASE traces
since they drive the power train MOSFETs with short,
high current pulses. It is important to size them as large
and short as possible to reduce their overall impedance
and inductance. Extra care should be given to the LGATE
traces in particular since keeping their impedance and
inductance low helps to significantly reduce the possibility
of shoot through.
When placing the MOSFETs, try to keep the source of
the upper MOSFETs and the drain of the lower MOSFETs
as close to each other as possible. Input bulk capacitors
should be placed close to the drain of the upper MOSFETs
and the source of the lower MOSFETs.
Locate the output inductors and output capacitors between
the MOSFETs and the load. Route high-speed switching
nodes away from sensitive analog areas (ISP, ISN, FB,
FBRTN, COMP, ADJ, OFS, IMAX.....)
Keep the routing of the bootstrap capacitor short between
BOOT and PHASE.
Place the snubber R&C as close as possible to the lower
MOSFETs of each phase.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-48L 7x7 package, the thermal resistance, θJA, is
31°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (31°C/W) = 3.226W for
WQFN-48L 7x7 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 15 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0
Four-Layer PCB
25
50
75
100
125
Ambient Temperature (°C)
Figure 15. Derating Curve of Maximum Power
Dissipation
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
20
is a registered trademark of Richtek Technology Corporation.
DS8868A-00 May 2012
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