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UTC571

LINEAR INTEGRATED CIRCUIT / COMPANDER

Unisonic Technologies 

UTC571

LINEAR INTEGRATED CIRCUIT

BASIC CIRCUIT HOOK-UP AND OPERATION

THD TRIM

R3

INVIN

R2

20K

GIN

3.14

R1

10K

RECTIN

2.15

8.9

G

IG

6.11

5.12

R3

20K

VREE

R4

1.8V

30K

VCC PIN 13

GND PIN 4

1.16

CRECT

Figure 2. Chip Block Diagram

OUTPUT

7.10

Figure 2 shows the block diagram of one half of the chip, (there are two identical channels on the IC). The full-

wave averaging rectifier provides a gain control current, IG , for the variable gain (∆G) cell. The output of the DG

cell is a current which is fed to the summing node of the operational amplifier. Resistors are provided to establish

circuit gain and set the output DC bias.

The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at

some voltage above ground. An internal band gap voltage reference provides a very stable, low noise 1.8V

reference denoted VREF . The non-inverting input of the op amp is tied to VREF , and the summing nodes of the

rectifier and ∆G cell (located at the right of R1 and R2) have the same potential. The THD trim pin is also the VREF

potential.

R3

CIN1

R2

G

VOUT

VIN

CIN2

R1

R4

VREF

NOTE: GAIN=

2R3VIN (avg)

R1R2IB

IB=140­A

CRECT

Figure 3. Basic Expander

Figure 3 shows how the circuit is hooked up to realize an expandor. The input signal, VIN is applied to the inputs

of both the rectifier and the ∆G cell. When the input signal drops by 6dB, the gain control current will drop by a

factor of 2, and so the gain will drop 6dB. The output level at VOUT will thus drop 12dB, giving us the desired 2 to 1

expansion.

YOUW ANG ELECTRONICS CO.LTD

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