ALC5624-GR 데이터 시트보기 (PDF) - Realtek Semiconductor
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ALC5624-GR Datasheet PDF : 78 Pages
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ALC5624
Datasheet
7.3. Clocking
The Stereo_SYSCLK can be selected from MCLK or PLL. This means MCLK is always provided
externally, and the driver should arrange the clock of each block and setup each divider.
EXTCLK can be output by setting Extclk_out_en =1 & pow_extclk=1. The output frequency is
determined by MCLK and the setting of Extclk_out_sel.
7.3.1. Phase-Locked Loop
A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. The
source of the PLL can be set to MCLK or BCLK by setting pll_sour_sel.
The driver can set up the PLL to output a frequency close to the SYSCLK.
The PLL transmit formula is:
FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}
MCLK
13
3.6864
2.048
4.096
12
15.36
16
19.2
19.68
Table 8.
N
66
78
94
70
80
81
78
80
78
Clock Setting Table for 48K (Unit: MHz)
M
FVCO
K
7
98.222
2
1
98.304
2
0
98.304
2
1
98.304
2
8
98.4
2
11
98.068
2
11
98.462
2
14
98.4
2
14
98.4
2
FOUT
24.555
24.576
24.576
24.576
24.6
24.517
24.615
24.6
24.6
Hand-Held Multimedia I2S Audio Codec
10
Track ID: JATR-1076-21 Rev. 1.3
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