NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency.
The Mode Register 2 is written by asserting low on , , , high on BA1 and low on BA0 and BA2, while
controlling the states of address pins according to the table below.
Fig. 10: MR2 Definition
REV 1.2
May. 2011
CONSUMER DRAM
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