NT5CB128M8DN 데이터 시트보기 (PDF) - Nanya Technology

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NT5CB128M8DN

1Gb DDR3 D-die SDRAM

Nanya Technology 

NT5CB128M8DN/NT5CB64M16DP

NT5CC128M8DN/NT5CC64M16DP

1Gb DDR3 D-die SDRAM

Mode Register MR3

The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on , Γ

, , high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table

below.

Fig. 11: MR3 Definition

Address Filed

BA2 BA 1 BA0 A13 A12 A11 A10 A9 A8 A 7 A6 A5 A4 A3 A2 A 1 A0

MRS mode

BA1 BA 0

MRS

mode

00

MR 0

01

MR1

10

MR2

11

MR3

MPR Operation

A2

MPR

0

Normal Operation

1

Dataflow fromMPR

MPR Location

A1 A0

MPR Location

0 0 PredefinedPattern2*

01

RFU

10

RFU

11

RFU

Note:BA2 ,A3-A13 are reserved for future use and mustbe

set to 0when programming theMR.

The predefined pattern will be used for read synchronization.

When MPR control is set for normal operation (MR3 A[2] =0) then

MR3 A[1:0] will be ignored.

REV 1.2

May. 2011

CONSUMER DRAM

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