BD63536FJ 데이터 시트보기 (PDF) - ROHM Semiconductor
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BD63536FJ Datasheet PDF : 17 Pages
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BD63536FJ
Technical Note
○CS: Current detection comparator input pin
The CS pin is an input pin of overcurrent detection circuit comparator. This IC has a built-in overcurent detection circuit
(current limit function) used to turn OFF output current if an abnormal overcurrent such as short-circuited output current flows
through the IC. This circuit monitors the currents of external FET such as current-sense resistor to input them to the CS pin.
When a voltage input to the CS pin reaches “VCC voltage 0.15V (typ)”, the current limit function will be activated. And when
it reaches the current limit voltage, the CS pin will turn OFF output current according to the set resistance and current values.
Subsequently, the pin will be automatically reset when the OSC pin reaches its peak voltage. As just described, the CS pin is
of the automatic resetting type. The CS pin is reset at the peak voltage of the OSC pin and, when the voltage reaches the set
current limit voltage, reset at the same peak voltage again. Then, the CS pin repeats such resetting cycle. Since
superimposing noises onto this pin may cause malfunctions, masking time of approximately 300ns has been internally set. In
addition, it is possible to prevent noises form jumping in the CS pin by adding a capacitor to this pin. Since delay time of
approximately 700ns including the said masking time of approximately 300ns is provided after the current limit is input until it
reaches the GATE pin, if the IC is controlled at a duty cycle of 700ns or less, the current limit function will not be activated.
Normally, no current setting seems to be made to the extent that the CS pin reaches the current limit voltage in the period of
approximately 700ns. However, pay utmost attention to the current setting because it also depends on the external FET. If
the overcurrent detection circuit is not used, short-circuit the CS pin to the VCC pin. If a current exceeds the absolute
maximum rating of the CS pin, the IC may break down. To avoid this, pay utmost attention to the current.
A current for the current limit function is set to “0.15V Resistance”. For example, when resistance is 75m, the set current
for the current limit function will come to “2A”.
OSC
CS
GATE
Fig.16 Current limit operation
If a voltage to be input to the CS pin falls below “VCC voltage 1V (typ)”, the gate-off function will be activated to turn OFF
output current. When the CS pin exceeds a voltage of “VCC voltage 1V (typ)”, the output current will be reset by the soft
start function.
○SOFT START
This IC has a built-in soft start function. This function is used to generate a clock in sync with oscillation inside the IC and
operate the internal 6bitDAC with this clock. Soft start time depends on the oscillation frequency. Taking a frequency 8 times
as high as the oscillation frequency as a reference clock, raise the output voltage at a rate of 40mV/count. The output voltage
will exceed approximately 1.25V at 32 counts. For example, when oscillation frequency fOSC is set to 100 kHz, a period of
time required to raise the voltage from 0V to 1.25V will come to approximately 2.56ms from “10µs 8 32 counts”.
Soft start signal
Internal clock
UVLO
OSC
Enlargement of internal clock generation
Fig.17 Soft start operation
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9/16
2009.11 - Rev.A
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