BD82B65 데이터 시트보기 (PDF) - Intel
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BD82B65 Datasheet PDF : 934 Pages
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5.1.6
PCI-to-PCI Bridge Model ..................................................................... 122
5.1.7
IDSEL to Device Number Mapping........................................................ 123
5.1.8
Standard PCI Bus Configuration Mechanism .......................................... 123
5.1.9
PCI Legacy Mode ............................................................................... 123
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 124
5.2.1
Interrupt Generation.......................................................................... 124
5.2.2
Power Management ........................................................................... 125
5.2.2.1 S3/S4/S5 Support .............................................................. 125
5.2.2.2 Resuming from Suspended State.......................................... 125
5.2.2.3 Device Initiated PM_PME Message ........................................ 125
5.2.2.4 SMI/SCI Generation ........................................................... 126
5.2.3
SERR# Generation............................................................................. 126
5.2.4
Hot-Plug .......................................................................................... 126
5.2.4.1 Presence Detection............................................................. 126
5.2.4.2 Message Generation ........................................................... 127
5.2.4.3 Attention Button Detection .................................................. 127
5.2.4.4 SMI/SCI Generation ........................................................... 127
5.3 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 128
5.3.1
GbE PCI Express* Bus Interface .......................................................... 130
5.3.1.1 Transaction Layer............................................................... 130
5.3.1.2 Data Alignment.................................................................. 130
5.3.1.3 Configuration Request Retry Status ...................................... 130
5.3.2
Error Events and Error Reporting ......................................................... 131
5.3.2.1 Data Parity Error ................................................................ 131
5.3.2.2 Completion with Unsuccessful Completion Status.................... 131
5.3.3
Ethernet Interface ............................................................................. 131
5.3.3.1 82579 LAN PHY Interface .................................................... 131
5.3.4
PCI Power Management...................................................................... 132
5.3.4.1 Wake Up ........................................................................... 132
5.3.5
Configurable LEDs ............................................................................. 134
5.3.6
Function Level Reset Support (FLR) ..................................................... 135
5.3.6.1 FLR Steps ......................................................................... 135
5.4 LPC Bridge (with System and Management Functions) (D31:F0)............................. 136
5.4.1
LPC Interface .................................................................................... 136
5.4.1.1 LPC Cycle Types................................................................. 137
5.4.1.2 Start Field Definition........................................................... 137
5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR) ............................... 138
5.4.1.4 Size ................................................................................. 138
5.4.1.5 SYNC................................................................................ 138
5.4.1.6 SYNC Time-Out.................................................................. 139
5.4.1.7 SYNC Error Indication ......................................................... 139
5.4.1.8 LFRAME# Usage................................................................. 139
5.4.1.9 I/O Cycles......................................................................... 139
5.4.1.10 Bus Master Cycles .............................................................. 140
5.4.1.11 LPC Power Management ...................................................... 140
5.4.1.12 Configuration and PCH Implications ...................................... 140
5.5 DMA Operation (D31:F0) .................................................................................. 141
5.5.1
Channel Priority ................................................................................ 141
5.5.1.1 Fixed Priority ..................................................................... 141
5.5.1.2 Rotating Priority................................................................. 142
5.5.2
Address Compatibility Mode ................................................................ 142
5.5.3
Summary of DMA Transfer Sizes.......................................................... 142
5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count
by Words .......................................................................... 142
5.5.4
Autoinitialize..................................................................................... 143
5.5.5
Software Commands.......................................................................... 143
5.6 LPC DMA ........................................................................................................ 144
5.6.1
Asserting DMA Requests..................................................................... 144
5.6.2
Abandoning DMA Requests ................................................................. 145
5.6.3
General Flow of DMA Transfers............................................................ 145
5.6.4
Terminal Count ................................................................................. 145
5.6.5
Verify Mode ...................................................................................... 146
5.6.6
DMA Request Deassertion................................................................... 146
5.6.7
SYNC Field / LDRQ# Rules .................................................................. 147
5.7 8254 Timers (D31:F0) ...................................................................................... 147
5.7.1
Timer Programming ........................................................................... 148
5.7.2
Reading from the Interval Timer.......................................................... 149
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