BD82B65 데이터 시트보기 (PDF) - Intel
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BD82B65 Datasheet PDF : 934 Pages
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5.8
5.9
5.10
5.11
5.12
5.13
5.7.2.1 Simple Read ..................................................................... 149
5.7.2.2 Counter Latch Command .................................................... 149
5.7.2.3 Read Back Command ......................................................... 149
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 150
5.8.1
Interrupt Handling ............................................................................ 151
5.8.1.1 Generating Interrupts......................................................... 151
5.8.1.2 Acknowledging Interrupts ................................................... 151
5.8.1.3 Hardware/Software Interrupt Sequence ................................ 152
5.8.2
Initialization Command Words (ICWx) ................................................. 152
5.8.2.1 ICW1 ............................................................................... 152
5.8.2.2 ICW2 ............................................................................... 153
5.8.2.3 ICW3 ............................................................................... 153
5.8.2.4 ICW4 ............................................................................... 153
5.8.3
Operation Command Words (OCW) ..................................................... 153
5.8.4
Modes of Operation ........................................................................... 153
5.8.4.1 Fully Nested Mode ............................................................. 153
5.8.4.2 Special Fully-Nested Mode .................................................. 154
5.8.4.3 Automatic Rotation Mode (Equal Priority Devices) .................. 154
5.8.4.4 Specific Rotation Mode (Specific Priority) .............................. 154
5.8.4.5 Poll Mode.......................................................................... 154
5.8.4.6 Cascade Mode ................................................................... 155
5.8.4.7 Edge and Level Triggered Mode ........................................... 155
5.8.4.8 End of Interrupt (EOI) Operations ........................................ 155
5.8.4.9 Normal End of Interrupt ..................................................... 155
5.8.4.10 Automatic End of Interrupt Mode ......................................... 155
5.8.5
Masking Interrupts ............................................................................ 156
5.8.5.1 Masking on an Individual Interrupt Request........................... 156
5.8.5.2 Special Mask Mode............................................................. 156
5.8.6
Steering PCI Interrupts...................................................................... 156
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 157
5.9.1
Interrupt Handling ............................................................................ 157
5.9.2
Interrupt Mapping ............................................................................. 157
5.9.3
PCI / PCI Express* Message-Based Interrupts....................................... 158
5.9.4
IOxAPIC Address Remapping .............................................................. 158
5.9.5
External Interrupt Controller Support................................................... 158
Serial Interrupt (D31:F0) ................................................................................. 159
5.10.1 Start Frame ..................................................................................... 159
5.10.2 Data Frames .................................................................................... 160
5.10.3 Stop Frame ...................................................................................... 160
5.10.4 Specific Interrupts Not Supported Using SERIRQ ................................... 160
5.10.5 Data Frame Format ........................................................................... 161
Real Time Clock (D31:F0)................................................................................. 162
5.11.1 Update Cycles .................................................................................. 162
5.11.2 Interrupts ........................................................................................ 163
5.11.3 Lockable RAM Ranges ........................................................................ 163
5.11.4 Century Rollover ............................................................................... 163
5.11.5 Clearing Battery-Backed RTC RAM....................................................... 163
Processor Interface (D31:F0) ............................................................................ 165
5.12.1 Processor Interface Signals and VLW Messages ..................................... 165
5.12.1.1 A20M# (Mask A20) / A20GATE ............................................ 165
5.12.1.2 INIT (Initialization) ............................................................ 166
5.12.1.3 FERR# (Numeric Coprocessor Error)..................................... 166
5.12.1.4 NMI (Non-Maskable Interrupt)............................................. 167
5.12.1.5 Processor Power Good (PROCPWRGD) .................................. 167
5.12.2 Dual-Processor Issues ....................................................................... 167
5.12.2.1 Usage Differences.............................................................. 167
5.12.3 Virtual Legacy Wire (VLW) Messages ................................................... 167
Power Management ......................................................................................... 168
5.13.1 Features .......................................................................................... 168
5.13.2 PCH and System Power States ............................................................ 168
5.13.3 System Power Planes ........................................................................ 170
5.13.4 SMI#/SCI Generation ........................................................................ 171
5.13.4.1 PCI Express* SCI............................................................... 173
5.13.4.2 PCI Express* Hot-Plug........................................................ 173
5.13.5 C-States .......................................................................................... 173
5.13.6 Dynamic PCI Clock Control (Mobile Only) ............................................. 173
5.13.6.1 Conditions for Checking the PCI Clock .................................. 173
Datasheet
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