BD82B65 데이터 시트보기 (PDF) - Intel
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BD82B65 Datasheet PDF : 934 Pages
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5.14
5.15
5.16
5.13.6.2 Conditions for Maintaining the PCI Clock................................ 174
5.13.6.3 Conditions for Stopping the PCI Clock ................................... 174
5.13.6.4 Conditions for Re-Starting the PCI Clock................................ 174
5.13.6.5 LPC Devices and CLKRUN# .................................................. 174
5.13.7 Sleep States ..................................................................................... 174
5.13.7.1 Sleep State Overview ......................................................... 174
5.13.7.2 Initiating Sleep State .......................................................... 175
5.13.7.3 Exiting Sleep States ........................................................... 175
5.13.7.4 PCI Express* WAKE# Signal and PME Event Message.............. 177
5.13.7.5 Sx-G3-Sx, Handling Power Failures....................................... 178
5.13.7.6 Deep S4/S5....................................................................... 179
5.13.8 Event Input Signals and Their Usage .................................................... 180
5.13.8.1 PWRBTN# (Power Button) ................................................... 180
5.13.8.2 RI# (Ring Indicator) ........................................................... 181
5.13.8.3 PME# (PCI Power Management Event) .................................. 181
5.13.8.4 SYS_RESET# Signal ........................................................... 182
5.13.8.5 THRMTRIP# Signal ............................................................. 182
5.13.9 ALT Access Mode ............................................................................... 183
5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode........ 184
5.13.9.2 PIC Reserved Bits............................................................... 186
5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode........ 186
5.13.10 System Power Supplies, Planes, and Signals ......................................... 187
5.13.10.1 Power Plane Control with SLP_S3#,
SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN# ......................... 187
5.13.10.2 SLP_S4# and Suspend-To-RAM Sequencing........................... 187
5.13.10.3 PWROK Signal ................................................................... 187
5.13.10.4 BATLOW# (Battery Low) (Mobile Only) ................................. 188
5.13.10.5 SLP_LAN# Pin Behavior ...................................................... 188
5.13.10.6 RTCRST# and SRTCRST#.................................................... 188
5.13.11 Clock Generators............................................................................... 188
5.13.12 Legacy Power Management Theory of Operation .................................... 189
5.13.12.1 APM Power Management (Desktop Only) ............................... 189
5.13.12.2 Mobile APM Power Management (Mobile Only)........................ 189
5.13.13 Reset Behavior.................................................................................. 189
System Management (D31:F0) .......................................................................... 192
5.14.1 Theory of Operation........................................................................... 192
5.14.1.1 Detecting a System Lockup ................................................. 192
5.14.1.2 Handling an Intruder .......................................................... 193
5.14.1.3 Detecting Improper Flash Programming ................................ 193
5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus............... 193
5.14.2 TCO Modes ....................................................................................... 194
5.14.2.1 TCO Legacy/Compatible Mode.............................................. 194
5.14.2.2 Advanced TCO Mode........................................................... 195
General Purpose I/O (D31:F0) ........................................................................... 196
5.15.1 Power Wells...................................................................................... 196
5.15.2 SMI# SCI and NMI Routing................................................................. 196
5.15.3 Triggering ........................................................................................ 196
5.15.4 GPIO Registers Lockdown ................................................................... 196
5.15.5 Serial POST Codes over GPIO.............................................................. 197
5.15.5.1 Theory of Operation ........................................................... 197
5.15.5.2 Serial Message Format........................................................ 198
SATA Host Controller (D31:F2, F5)..................................................................... 199
5.16.1 SATA 6 Gb/s Support ......................................................................... 200
5.16.2 SATA Feature Support........................................................................ 200
5.16.3 Theory of Operation........................................................................... 201
5.16.3.1 Standard ATA Emulation ..................................................... 201
5.16.3.2 48-Bit LBA Operation .......................................................... 201
5.16.4 SATA Swap Bay Support..................................................................... 201
5.16.5 Hot Plug Operation ............................................................................ 201
5.16.5.1 Low Power Device Presence Detection................................... 201
5.16.6 Function Level Reset Support (FLR) ..................................................... 202
5.16.7
5.16.8
5.16.6.1 FLR Steps ......................................................................... 202
Intel® Rapid Storage Technology Configuration ..................................... 202
5.16.7.1 Intel® Rapid Storage Manager RAID Option ROM.................... 203
Intel® Smart Response Technology...................................................... 203
5.16.9 Power Management Operation............................................................. 203
5.16.9.1 Power State Mappings ........................................................ 203
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