ISL6260C 데이터 시트보기 (PDF) - Intersil

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ISL6260C

Multiphase PWM Regulator for IMVP-6+ Mobile CPUs

Intersil 

ISL6260C

Typical Operating Performance (Continued)

VOUT

COMP PIN

FIGURE 19. TRANSIENT LOAD RESPONSE, 40A LOAD STEP

@ 200A/µs, 3 PHASE

FIGURE 20. TRANSIENT LOAD 3 PHASE OPERATION -

CURRENT BALANCE

FIGURE 21. TRANSIENT LOAD 3 PHASE OPERATION, ZOOM

OF RISING EDGE CURRENT BALANCE

VID MSB

VOUT

FIGURE 22. TRANSIENT LOAD 3 PHASE OPERATION, ZOOM

OF FALLING EDGE CURRENT BALANCE

VID MSB

VOUT

FIGURE 23. IVID MSB BIT CHANGE FROM 1.4375V TO 0.65V

SHOWING 9mV/µs SLEW RATE, DPRSLPVR = 0,

DPRSTP# = 1

10

FIGURE 24. SLEW RATE ENTERING C4, VID MSB BIT

CHANGE FROM 1.4375V TO 0.65V SHOWING

2mV/µs SLEW RATE, DPRSLPVR = 1, DPRSTP# = 0

FN9259.3

June 21, 2010

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