Q67006-A9309 데이터 시트보기 (PDF) - Siemens AG

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Q67006-A9309

Dual Low-Drop Voltage Regulator

Siemens AG 

TLE 4470

P-DSO-14-4

Pin No. Symbol

1

D

2

3, 4, 5

6

DIS

GND

RQ

7

SQ

8

Q1

9

Q2

10, 11, 12 GND

13

I

14

SI

Function

Reset delay; connect a capacitor CD to GND for delay time

adjustment

Disable input main regulator; Q2 disabled with high signal

Ground

Reset output; the open collector output is connected to Q1

via an integrated 30 kΩ resistor

Sense output; the open collector output is connected to Q1

via an integrated 30 kΩ resistor

Stand-by regulator output voltage; block to GND with a

capacitor, CQ1 ≥ 6 µF, ESR < 10 Ω at 10 kHz

Main regulator output voltage; 5 V output tracking to Q1,

block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 10 Ω at

10 kHz

Ground

Main and stand-by regulator input voltage; block to GND

directly at the IC with a ceramic capacitor

Sense comparator input

RADJ

ADJ2

Reset switching threshold adjust not available in P-DSO-14-4 package. Reset

is always triggered at the internal threshold.

Main regulator adjust input is internally connected to VQ2

Semiconductor Group

4

1998-11-01

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