KSZ8081RNA 데이터 시트보기 (PDF) - Micrel

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KSZ8081RNA

10Base-T/100Base-TX PHY with RMII Support

Micrel 

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

List of Figures

Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 14

Figure 2. KSZ8081RNA/RND RMII Interface (RMII – 25MHz Clock Mode) ........................................................................ 17

Figure 3. KSZ8081RNA/RND RMII Interface (RMII – 50MHz Clock Mode) ........................................................................ 17

Figure 4. KSZ8081RNA/RND and KSZ8081RNA/RND RMII Back-to-Back Copper Repeater ........................................... 18

Figure 5. Typical Straight Cable Connection ....................................................................................................................... 20

Figure 6. Typical Crossover Cable Connection ................................................................................................................... 21

Figure 7. Local (Digital) Loopback ....................................................................................................................................... 21

Figure 8. Remote (Analog) Loopback .................................................................................................................................. 22

Figure 9. KSZ8081RNA/RND Power and Ground Connections .......................................................................................... 26

Figure 10. RMII Timing – Data Received from RMII ............................................................................................................ 41

Figure 11. RMII Timing – Data Input to RMII ....................................................................................................................... 41

Figure 12. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 42

Figure 13. MDC/MDIO Timing.............................................................................................................................................. 43

Figure 14. Power-Up/Reset Timing...................................................................................................................................... 44

Figure 15. Recommended Reset Circuit .............................................................................................................................. 45

Figure 16. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 45

Figure 17. Reference Circuits for LED Strapping Pins......................................................................................................... 46

Figure 18. 25MHz Crystal/Oscillator Reference Clock Connection ..................................................................................... 47

Figure 19. 50MHz Oscillator Reference Clock Connection ................................................................................................. 47

Figure 20. Typical Magnetic Interface Circuit....................................................................................................................... 48

Figure 21. Recommended Land Pattern, 24-Pin (4mm × 4mm) QFN ................................................................................. 50

February 6, 2014

6

Revision 1.1

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