3692 데이터 시트보기 (PDF) - Linear Technology

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3692

Monolithic Dual Tracking 3.5A Step-Down Switching Regulator

Linear Technology 

LT3692

BLOCK DIAGRAM

VIN1

SHDN1

2.5V

12µA

SS1

VC1

2.5V

ILIM1

12µA

RLIM

2.5V

RT/SYNC

12µA

R3

2.5V

DIV

RDIV

12µA

1.3V +

–

–

+

90mV

38V

THERMAL

SHUTDOWN

–

+

PRE

S

Q

R

S PRE

Q

R

CHANNEL 1

DROPOUT

ENHANCEMENT

DRIVER

CIRCUITRY

SLOPE

COMPENSATION

0.806V

0.72V +

–

OSCILLATOR

AND AGC

CLK1

MASTER CLOCK

CLK2 TO CHANNEL 2

VIN1 +

2.8V –

INTERNAL

2.5V

REGULATOR

AND

REFERENCES

Figure 1. LT3692 Block Diagram

VIN1

BST1

SW1

IND1

VOUT1

R1

FB1

CMPI1

R2

CMPO1

TJ

CLKOUT

GND

3692 F01

The LT3692 is a dual channel, constant frequency, current

mode buck converter with internal 3.5A switches. Each

channel can be independently controlled with the exception

that VIN1 must be above the 2.8V undervoltage lockout

threshold to power the common internal regulator, oscil-

lator and thermometer circuitry.

If the SHDN1 pin is taken below its 1.3V threshold the

LT3692 will be placed in a low quiescent current mode.

In this mode the LT3692 typically draws 6µA from VIN1

and <1µA from VIN2. When the SHDN pin is driven above

1.3V, the internal bias circuits turn on generating an in-

ternal regulated voltage, 0.806VFB, 12µA RT/SYNC, DIV

and ILIM current references, and a POR signal which sets

the soft-start latch.

Once the internal reference reaches its regulation point,

the internal oscillator will start generating a master clock

signal for the two regulators at a frequency determined

by the voltage present at the RT/SYNC pin. The channel 1

clock is then divided by 1, 2, 4 or 8 depending on the

voltage present at the DIV pin. Channel 2’s clock runs at

the master clock frequency with a 180° phase shift from

channel 1.

Alternatively, if a synchronization signal is detected by

the LT3692 the RT/SYNC pin, the master clock will be

generated at the incoming frequency on the rising edge

of the synchronization pulse with channel 1 in phase with

the synchronization signal. Frequency division and phase

remains the same as the internally generated master clock.

3692f

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