BD82HM55QMNT 데이터 시트보기 (PDF) - Intel
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BD82HM55QMNT Datasheet PDF : 934 Pages
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5.8
5.9
5.10
5.11
5.12
5.13
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 147
5.8.1 Interrupt Handling................................................................................ 148
5.8.1.1 Generating Interrupts.............................................................. 148
5.8.1.2 Acknowledging Interrupts ........................................................ 148
5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 149
5.8.2 Initialization Command Words (ICWx) ..................................................... 149
5.8.2.1 ICW1 .................................................................................... 149
5.8.2.2 ICW2 .................................................................................... 150
5.8.2.3 ICW3 .................................................................................... 150
5.8.2.4 ICW4 .................................................................................... 150
5.8.3 Operation Command Words (OCW) ......................................................... 150
5.8.4 Modes of Operation .............................................................................. 150
5.8.4.1 Fully Nested Mode................................................................... 150
5.8.4.2 Special Fully-Nested Mode........................................................ 151
5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 151
5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 151
5.8.4.5 Poll Mode............................................................................... 151
5.8.4.6 Cascade Mode ........................................................................ 152
5.8.4.7 Edge and Level Triggered Mode ................................................ 152
5.8.4.8 End of Interrupt (EOI) Operations ............................................. 152
5.8.4.9 Normal End of Interrupt........................................................... 152
5.8.4.10 Automatic End of Interrupt Mode .............................................. 152
5.8.5 Masking Interrupts ............................................................................... 153
5.8.5.1 Masking on an Individual Interrupt Request................................ 153
5.8.5.2 Special Mask Mode.................................................................. 153
5.8.6 Steering PCI Interrupts ......................................................................... 153
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 154
5.9.1 Interrupt Handling................................................................................ 154
5.9.2 Interrupt Mapping ................................................................................ 154
5.9.3 PCI / PCI Express* Message-Based Interrupts .......................................... 155
5.9.4 IOxAPIC Address Remapping ................................................................. 155
5.9.5 External Interrupt Controller Support ...................................................... 155
Serial Interrupt (D31:F0) ................................................................................. 156
5.10.1 Start Frame......................................................................................... 156
5.10.2 Data Frames........................................................................................ 157
5.10.3 Stop Frame ......................................................................................... 157
5.10.4 Specific Interrupts Not Supported Using SERIRQ ...................................... 157
5.10.5 Data Frame Format .............................................................................. 158
Real Time Clock (D31:F0)................................................................................. 159
5.11.1 Update Cycles...................................................................................... 159
5.11.2 Interrupts ........................................................................................... 160
5.11.3 Lockable RAM Ranges ........................................................................... 160
5.11.4 Century Rollover .................................................................................. 160
5.11.5 Clearing Battery-Backed RTC RAM .......................................................... 160
Processor Interface (D31:F0) ............................................................................ 162
5.12.1 Processor Interface Signals and VLW Messages ........................................ 162
5.12.1.1 A20M# (Mask A20) / A20GATE ................................................. 162
5.12.1.2 INIT (Initialization) ................................................................. 163
5.12.1.3 FERR# (Numeric Coprocessor Error) .......................................... 163
5.12.1.4 NMI (Non-Maskable Interrupt) .................................................. 164
5.12.1.5 Processor Power Good (PROCPWRGD) ....................................... 164
5.12.2 Dual-Processor Issues........................................................................... 164
5.12.2.1 Usage Differences ................................................................... 164
5.12.3 Virtual Legacy Wire (VLW) Messages....................................................... 164
Power Management (D31:F0) ........................................................................... 165
5.13.1 Features ............................................................................................. 165
5.13.2 PCH and System Power States ............................................................... 165
5.13.3 System Power Planes ............................................................................ 167
5.13.4 SMI#/SCI Generation ........................................................................... 167
5.13.4.1 PCI Express* SCI.................................................................... 170
5.13.4.2 PCI Express* Hot-Plug............................................................. 170
5.13.5 C-States ............................................................................................. 170
5.13.6 Dynamic PCI Clock Control (Mobile Only)................................................. 170
5.13.6.1 Conditions for Checking the PCI Clock........................................ 171
5.13.6.2 Conditions for Maintaining the PCI Clock .................................... 171
5.13.6.3 Conditions for Stopping the PCI Clock ........................................ 171
5.13.6.4 Conditions for Re-Starting the PCI Clock .................................... 171
Datasheet
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