BD82HM55QMNT 데이터 시트보기 (PDF) - Intel
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BD82HM55QMNT Datasheet PDF : 934 Pages
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5.29
5.28.3 Support for Function Level Reset (FLR) in Intel® 5 Series
Chipset and Intel® 3400 Series Chipset................................................... 272
5.28.4 Virtualization Support for PCH’s IOxAPIC ................................................. 273
5.28.5 Virtualization Support for High Precision Event Timer (HPET)...................... 273
Intel® 5 Series Chipset and Intel® 3400 Series Chipset Platform Clocks.................. 274
5.29.1 Platform Clocking Requirements ............................................................. 274
6 Ballout Definition................................................................................................... 275
6.1 PCH Desktop Ballout ........................................................................................ 275
6.2 PCH Ballout Mobile Ballout ................................................................................ 286
6.3 PCH Ballout Small Form Factor Ballout ............................................................... 298
7 Package Information ............................................................................................. 311
7.1 PCH package (Desktop Only) ............................................................................ 311
7.2 PCH package (Mobile Only)............................................................................... 313
7.3 PCH package (Mobile SFF Only)......................................................................... 315
8
Electrical Characteristics ....................................................................................... 317
8.1 Thermal Specifications ..................................................................................... 317
8.1.1 Desktop Storage Specifications and Thermal Design Power (TDP) ............... 317
8.1.2 Mobile Storage Specifications and Thermal Design Power (TDP) .................. 317
8.2 Absolute Maximum Ratings............................................................................... 318
8.3 Intel® 5 Series Chipset and Intel® 3400 Series Chipset Power Supply range ........... 318
8.4 General DC Characteristics ............................................................................... 319
8.5 Display DC Characteristics ................................................................................ 332
8.6 AC Characteristics ........................................................................................... 334
8.7 Power Sequencing and Reset Signal Timings ....................................................... 349
8.8 Power Management Timing Diagrams................................................................. 352
8.9 AC Timing Diagrams ........................................................................................ 355
9
Register and Memory Mapping............................................................................... 365
9.1 PCI Devices and Functions................................................................................ 366
9.2 PCI Configuration Map ..................................................................................... 367
9.3 I/O Map ......................................................................................................... 367
9.3.1 Fixed I/O Address Ranges ..................................................................... 367
9.3.2 Variable I/O Decode Ranges .................................................................. 370
9.4 Memory Map................................................................................................... 371
9.4.1 Boot-Block Update Scheme.................................................................... 373
10 Chipset Configuration Registers............................................................................. 375
10.1
Chipset Configuration Registers (Memory Space) ................................................. 375
10.1.1 V0CTL—Virtual Channel 0 Resource Control Register ................................. 378
10.1.2 V0STS—Virtual Channel 0 Resource Status Register .................................. 378
10.1.3 V1CTL—Virtual Channel 1 Resource Control Register ................................. 379
10.1.4 V1STS—Virtual Channel 1 Resource Status Register .................................. 379
10.1.5 CIR0—Chipset Initialization Register 0..................................................... 379
10.1.6 CIR1—Chipset Initialization Register 1..................................................... 380
10.1.7 REC—Root Error Command Register ....................................................... 380
10.1.8 ILCL—Internal Link Capabilities List Register ............................................ 380
10.1.9 LCAP—Link Capabilities Register ............................................................. 381
10.1.10LCTL—Link Control Register ................................................................... 381
10.1.11LSTS—Link Status Register .................................................................... 381
10.1.12BCR—Backbone Configuration Register.................................................... 382
10.1.13RPC—Root Port Configuration Register .................................................... 382
10.1.14DMIC—DMI Control Register .................................................................. 383
10.1.15RPFN—Root Port Function Number and Hide for PCI Express* Root Ports ..... 384
10.1.16FLRSTAT—FLR Pending Status Register ................................................... 385
10.1.17CIR5—Chipset Initialization Register 5..................................................... 386
10.1.18TRSR—Trap Status Register ................................................................... 386
10.1.19TRCR—Trapped Cycle Register ............................................................... 386
10.1.20TWDR—Trapped Write Data Register....................................................... 387
10.1.21IOTRn—I/O Trap Register (0-3).............................................................. 387
10.1.22DMC—DMI Miscellaneous Control Register ............................................... 388
10.1.23CIR6—Chipset Initialization Register 6..................................................... 388
10.1.24DMC2—DMI Miscellaneous Control Register 2 ........................................... 388
10.1.25TCTL—TCO Configuration Register .......................................................... 389
10.1.26D31IP—Device 31 Interrupt Pin Register.................................................. 390
10.1.27D30IP—Device 30 Interrupt Pin Register.................................................. 391
Datasheet
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