BD82HM55-SLGZS 데이터 시트보기 (PDF) - Intel
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BD82HM55-SLGZS Datasheet PDF : 956 Pages
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5.1.8
Standard PCI Bus Configuration Mechanism........................................... 127
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 127
5.2.1
Interrupt Generation .......................................................................... 128
5.2.2
Power Management............................................................................ 128
5.2.2.1
S3/S4/S5 Support ............................................................... 128
5.2.2.2
Resuming from Suspended State ........................................... 129
5.2.2.3
Device Initiated PM_PME Message.......................................... 129
5.2.2.4
SMI/SCI Generation ............................................................. 129
5.2.3
SERR# Generation ............................................................................. 130
5.2.4
Hot-Plug ........................................................................................... 130
5.2.4.1
Presence Detection .............................................................. 130
5.2.4.2
Message Generation............................................................. 131
5.2.4.3
Attention Button Detection.................................................... 131
5.2.4.4
SMI/SCI Generation ............................................................. 132
5.3 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 132
5.3.1
GbE PCI Express* Bus Interface........................................................... 134
5.3.1.1
Transaction Layer ................................................................ 134
5.3.1.2
Data Alignment ................................................................... 134
5.3.1.3
Configuration Request Retry Status........................................ 134
5.3.2
Error Events and Error Reporting ......................................................... 135
5.3.2.1
Data Parity Error ................................................................. 135
5.3.2.2
Completion with Unsuccessful Completion Status ..................... 135
5.3.3
Ethernet
5.3.3.1
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82577/82578 PHY Interface .................................................. 135
5.3.4
PCI Power Management ...................................................................... 136
5.3.4.1
Wake Up ............................................................................ 136
5.3.5
Configurable LEDs ............................................................................. 138
5.3.6
Function Level Reset Support (FLR)...................................................... 138
5.3.6.1
FLR Steps ........................................................................... 139
5.4 LPC Bridge (with System and Management Functions) (D31:F0)............................. 139
5.4.1
LPC Interface .................................................................................... 139
5.4.1.1
LPC Cycle Types .................................................................. 140
5.4.1.2
Start Field Definition ............................................................ 141
5.4.1.3
Cycle Type / Direction (CYCTYPE + DIR) ................................. 141
5.4.1.4
Size ................................................................................... 141
5.4.1.5
SYNC ................................................................................. 142
5.4.1.6
SYNC Time-Out ................................................................... 142
5.4.1.7
SYNC Error Indication........................................................... 142
5.4.1.8
LFRAME# Usage .................................................................. 142
5.4.1.9
I/O Cycles .......................................................................... 143
5.4.1.10 Bus Master Cycles................................................................ 143
5.4.1.11 LPC Power Management ....................................................... 143
5.4.1.12 Configuration and PCH Implications........................................ 143
5.5 DMA Operation (D31:F0) .................................................................................. 144
5.5.1
Channel Priority................................................................................. 144
5.5.1.1
Fixed Priority ...................................................................... 144
5.5.1.2
Rotating Priority .................................................................. 145
5.5.2
Address Compatibility Mode ................................................................ 145
5.5.3
Summary of DMA Transfer Sizes .......................................................... 145
5.5.3.1
Address Shifting When Programmed for 16-Bit I/O Count
by Words............................................................................ 145
5.5.4
Autoinitialize ..................................................................................... 146
5.5.5
Software Commands .......................................................................... 146
5.6 LPC DMA ........................................................................................................ 147
5.6.1
Asserting DMA Requests ..................................................................... 147
5.6.2
Abandoning DMA Requests.................................................................. 148
5.6.3
General Flow of DMA Transfers ............................................................ 148
5.6.4
Terminal Count.................................................................................. 148
5.6.5
Verify Mode ...................................................................................... 149
5.6.6
DMA Request De-assertion.................................................................. 149
5.6.7
SYNC Field / LDRQ# Rules .................................................................. 150
5.7 8254 Timers (D31:F0) ...................................................................................... 150
5.7.1
Timer Programming ........................................................................... 151
5.7.2
Reading from the Interval Timer .......................................................... 152
5.7.2.1
Simple Read ....................................................................... 152
5.7.2.2
Counter Latch Command ...................................................... 152
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