NJU6433B 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6433B

1/4 DUTY LCD DRIVER

Japan Radio Corporation  

NJU6433B

FUNCTIONAL DESCRIPTION

(1) Operation of each block

(1-1) Oscillation Circuit

The oscillation circuit operates by connecting external resistance (capacitance is incorporated).

This circuit provides the clock signal to both common and segment drivers.

(1-2) Divider Circuit

This circuit divides the oscillating signal to generate the common and segment timing.

(1-3) Shift-Register

When the CE terminal is "H" (Enable mode), the display data is transferred to the shift-register

synchronized by the shift clock on the SCL terminal.

(1-4) Latch Circuit and Segment Driver

When the CE signal falling, the display data is latched, and the data controls the segment signal of

display-on/off.

(1-5) Common Driver

The Common driver generates driving waveform to common terminal.

(1-6) Reset Circuit

The Reset circuit is type of detectable voltage. It resets internal circuit when the power turns on.

-4-

Ver.2012-10-23

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