MC3423 데이터 시트보기 (PDF) - Motorola => Freescale
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MC3423 Datasheet PDF : 8 Pages
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MC3423
Figure 7. Circuit Configuration for
Activating One MC3423 from Another
Figure 8. R1 versus Trip Voltage
30
+
1
Power
6
Supply
#1
7
–
Power
Supply
#2
R1 10k
1
5
+
Q1
1.0k
7
–
Note that both supplies have their negative output leads
tied together (i.e., both are positive supplies). If their
positive leads are common (two negative supplies) the
emitter of Q1 would be moved to the positive lead of supply
1 and R1 would therefore have to be resized to deliver the
appropriate drive to Q1.
R2 = 2.7 k
20
10
Typ
Max
Min
0
0
5.0
10
15
20
25
30
VT, TRIP VOLTAGE (V)
Figure 9. Minimum RG versus Supply Voltage
35
30
RG(min) = 0
if VCC < 11 V
25
Crowbar SCR Considerations
Referring to Figure 11, it can be seen that the crowbar
SCR, when activated, is subject to a large current surge from
the output capacitance, Cout. This capacitance consists of
the power supply output caps, the load’s decoupling caps,
and in the case of Figure 11A, the supply’s input filter caps.
This surge current is illustrated in Figure 12, and can cause
SCR failure or degradation by any one of three mechanisms:
di/dt, absolute peak surge, or I2t. The interrelationship of
these failure methods and the breadth of the applications
make specification of the SCR by the semiconductor
manufacturer difficult and expensive. Therefore, the designer
must empirically determine the SCR and circuit elements
which result in reliable and effective OVP operation.
However, an understanding of the factors which influence the
SCR’s di/dt and surge capabilities simplifies this task.
di/dt
As the gate region of the SCR is driven on, its area of
conduction takes a finite amount of time to grow, starting as a
very small region and gradually spreading. Since the anode
current flows through this turned–on gate region, very high
current densities can occur in the gate region if high anode
currents appear quickly (di/dt). This can result in immediate
destruction of the SCR or gradual degradation of its forward
blocking voltage capabilities – depending on the severity of
the occasion.
20
15
10
0 10 20 30 40 50 60 70 80
RG, GATE CURRENT LIMITING RESISTOR (Ω)
Figure 10. Capacitance versus
Minimum Overvoltage Duration
1 2 3 57 1
1.0
0.1
0.01
0.001
1
5
2
0.0001
1
0.001
0.01
0.1
1.0
10
td, DELAY TIME (ms)
MOTOROLA ANALOG IC DEVICE DATA
5
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