MC54HC4060A 데이터 시트보기 (PDF) - Motorola => Freescale
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MC54HC4060A Datasheet PDF : 11 Pages
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MC54/74HC4060A
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Negative–edge triggering clock input. A high–to–low tran-
sition on this input advances the state of the counter. Osc In
may be driven by an external clock source.
Reset (Pin 12)
Active–high reset. A high level applied to this input asynch-
ronously resets the counter to its zero state (forcing all Q out-
puts low) and disables the oscillator.
OUTPUTS
Q4—Q10, Q12–Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.
Osc Out 1, Osc Out 2 (Pins 9, 10)
Oscillator outputs. These pins are used in conjunction with
Osc In and the external components to form an oscillator
(See NO TAG and NO TAG). When Osc In is being driven
with an external clock source, Osc Out 1 and Osc Out 2 must
be left open circuited. With the crystal oscillator configuration
in Figure 6, Osc Out 2 must be left open circuited.
SWITCHING WAVEFORMS
tf
tr
90%
VCC
Osc In
50%
10%
GND
tw
1/fMAX
tPLH
tPHL
90%
Q 50%
10%
tTLH
tTHL
Reset
tPHL
Q
Osc In
tw
50%
50%
Figure 1.
Figure 2.
VCC
GND
trec
VCC
50%
GND
Qn
50%
tPLH
VCC
GND
tPHL
Qn+1
50%
Figure 3.
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
High–Speed CMOS Logic Data
3–5
DL129 — Rev 6
MOTOROLA
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