PM25LD010 데이터 시트보기 (PDF) - Unspecified

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PM25LD010

512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus

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CONNECTION DIAGRAMS

CE#

1

8

SO

2

7

Vcc

HOLD#

WP#

GND

3

6

4

5

8-Pin SOIC

SCK

SIO

Pm25LD512/010/ 020

CE# 1

SO 2

WP# 3

GND 4

8 Vcc

7 HOLD#

6 SCK

5 SIO

8-Contact WSON

CE#

1

SO

2

WP# 3

GND 4

8

Vcc

7

HOLD#

6

SCK

5

SIO

8-Pin TSSOP

CE# 1

SO 2

WP# 3

GND 4

8 Vcc

7 HOLD#

6 SCK

5 SIO

PIN DESCRIPTIONS

8-Pin PDIP

SYMBOL TYPE

DESCRIPTION

CE#

SCK

SIO

SO

GND

Vcc

WP#

HOLD#

INPUT

INPUT

INPUT/OUTPUT

OUTPUT

INPUT

INPUT

Chip Enable: CE# low activates the devices internal circuitries for

device operation. CE# high deselects the devices and switches into

standby mode to reduce the power consumption. When a device is not

selected, data will not be accepted via the serial input pin (SlO), and the

serial output pin (SO) will remain in a high impedance state.

Serial Data Clock

Serial Data Input/Output

Serial Data Output

Ground

Device Power Supply

Write Protect: A hardware program/erase protection for all or part of a

memory array. When the WP# pin is low, memory array write-protection depends

on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is

high, the devices are not write-protected.

Hold: Pause serial communication by the master device without resetting

the serial sequence.

Confidential information

Chingis Technology Corp.

3

DRAFT Date: August, 2010, Rev:0.4

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