PM25LD010 데이터 시트보기 (PDF) - Unspecified

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PM25LD010

512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus

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Pm25LD512/010/ 020

REGISTERS (CONTINUED)

Table 6. Status Register Bit Definition

Bit

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bits 5 - 6

Bit 7

Name

WIP

WEL

BP0

BP1

BP2

N/A

SRWD

Definition

Write In Progress Bit:

"0" indicates the device is ready

"1" indicates a write cycle is in progress and the device is busy

Write Enable Latch:

"0" indicates the device is not write enabled

"1" indicates the device is write enabled (default)

Block Protection Bit: (See Table 7 and Table 8 for details)

"0" indicates the specific blocks are not write-protected (default)

"1" indicates the specific blocks are write-protected

Reserved: Always "0"s

Status Register Write Disable: (See Table 9 for details)

"0" indicates the Status Register is not write-protected (default)

"1" indicates the Status Register is write-protected

Read-

/Write

R

R/W

R/W

N/A

R/W

Non-Volatile

bit

No

No

Yes

Yes

Table 8. Block Write Protect Bits for Pm25LD512/010/020

Status Register Bits

BP1

BP0

0

0

0

1

1

0

1

1

Pm25LD512A

Protected Memory Area

Pm25LD010A

Pm25LD020

None

None

None

None

None

All Blocks

000000h - 00FFFFh

Upper quarter (Block 3) Upper quarter (Block 3)

018000h - 01FFFFh

030000h - 03FFFFh

Upper half (Block 2 & 3) Upper half (Block 2 & 3)

010000h - 01FFFFh

020000h - 03FFFFh

All Blocks

All Blocks

000000h - 01FFFFh

000000h - 03FFFFh

Confidential information

Chingis Technology Corp.

8

DRAFT Date: August, 2010, Rev:0.4

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