UPD720133 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD720133

USB2.0 to IDE Bridge

NEC => Renesas Technology 

µPD720133

1. PIN INFORMATION

Pin Name

I/O

Buffer Type

Active Level

Function

XIN

I

XOUT

O

RESETB

I

IDECS(1:0)B

O (I/O)

IDEA(2:0)

O (I/O)

IDEINT

I

IDEDAKB

O (I/O)

IDEIORDY

I

IDEIORB

O (I/O)

IDEIOWB

O (I/O)

IDEDRQ

I

IDED(15:0)

I/O

IDERSTB

O (I/O)

CMB_BSY (GPIO7)

I/O

CMB_STATE (GPIO6) I/O

DPC (GPIO5)

I/O

SDA (PIO0)

I/O

SCL (PIO1)

I/O

VBUS

I

DP

I/O

DM

I/O

RSDP

O

RSDM

O

RPU

A

RREF

A

SCAN

I

TEST

I

AVDD25

VDD25

VDD33

AVSS

VSS

2.5 V Input

2.5 V Output

3.3 V Schmitt Input

5 V tolerant Output

5 V tolerant Output

5 V tolerant Input

5 V tolerant Output

5 V tolerant Input

5 V tolerant Output

5 V tolerant Output

5 V tolerant Input

5 V tolerant I/O

5 V tolerant Output

3.3 V I/O

3.3 V I/O

3.3 V I/O

3.3 V I/O

3.3 V I/O

5 V Schmitt Input Note

USB high speed D+ I/O

USB high speed D− I/O

USB full speed D+ Output

USB full speed D− Output

USB Pull-up control

Analog

3.3 V Input

3.3 V Input

Low

Low

High

Low

High

Low

Low

High

Low

System clock input or oscillator In

Oscillator out

Asynchronous reset signaling

IDE host chip select

IDE address bus

IDE interrupt request from device to host

IDE DMA acknowledge

IDE IO channel ready

IDE IO read strobe

IDE IO write strobe

IDE DMA request from device to host

IDE data bus

IDE reset from host to device

Combo IDE bus busy

Combo IDE bus state

Power control signaling for IDE device

Serial ROM data signaling

Serial ROM clock signaling

VBUS monitoring

USB’s high speed D+ signal

USB’s high speed D− signal

USB’s full speed D+ signal

USB’s full speed D− signal

USB’s 1.5 kΩ pull-up resistor control

Reference resistor

Scan mode control

Test mode setting

2.5 V VDD for Analog circuit

2.5 V VDD

3.3 V VDD

VSS for Analog circuit

VSS

Note

VBUS pin may be used to monitor for VBUS line even if VDD33, VDD25, and AVDD25 are shut off. The System

Designer must ensure that the input voltage level for VBUS pin is less than 3.0 V. [that is the absolute

maximum rating].

Remarks 1. “5 V tolerant“ means that the buffer is a 3.3 V buffer with 5 V tolerant circuit.

2. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. They should be

ignored under normal operation.

Preliminary Data Sheet S17100EJ2V0DS

5

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