S3C70F2 데이터 시트보기 (PDF) - Samsung

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S3C70F2

single-chip CMOS microcontroller

Samsung 

S3C70F2/C70F4/P70F4

PRODUCT OVERVIEW

Pin Name

Table 1-1. S3C70F2/C70F4 Pin Descriptions (Continued)

Pin

Type

Description

Quasi-interrupt input with falling edge detection

Number

26-28(28-30)

Share Pin

P6.0–P6.2

VDD

— Main power supply

30(32)

—

VSS

— Ground

1(1)

—

RESET

I

Reset signal

7(7)

—

TEST

I

Test signal input (must be connected to VSS)

4(4)

—

Xin, Xout

— Crystal or ceramic oscillator signal for system clock

3,2(3,2)

—

NOTE: Pin numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.

Table 1-2. Overview of S3C70F2/C70F4 Pin Data

SDIP Pin

Numbers

1

2,3

4

5,6

7

8-10

11-14

15-17

18-21

22-25

26-29

30

Pin

Names

VSS

Xout, Xin

TEST

P1.0, P1.1

RESET

P0.0 - P0.2

P2.0 - P2.3

P3.0 - P3.2

P4.0 - P4.3

P5.0 - P5.3

P6.0 - P6.3

VDD

Share

Pins







INT0, INT1



SCK, SO, SI

CIN0 - CIN3

TCL0, TCLO0,

CLO





KS0, KS1, KS2,

BUZ



I/O

Type





I

I

I

I/O

I

I/O

I/O

I/O

I/O



Reset

Value







Input



Input

Input

Input

Input

Input

Input



NOTE: I/O circuit type F-2 is implemented for P2.3 only.

Circuit

Type







A-3

B

D-1

F-1, F-2 (note)

D-1

E

E

D-1



1-11

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