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MP1482 데이터 시트보기 (PDF) - Monolithic Power Systems

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MP1482 Datasheet PDF : 12 Pages
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MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER
The worst-case condition occurs at VIN = 2VOUT,
where IC1 = ILOAD/2. For simplification, choose
the input capacitor whose RMS current rating
greater than half of the maximum load current.
The input capacitor can be electrolytic, tantalum
or ceramic. When using electrolytic or tantalum
capacitors, a small, high quality ceramic
capacitor, i.e. 0.1μF, should be placed as close
to the IC as possible. When using ceramic
capacitors, make sure that they have enough
capacitance to provide sufficient charge to
prevent excessive voltage ripple at input. The
input voltage ripple for low ESR capacitors can
be estimated by:
VIN
ILOAD
C1fS
VOUT
VIN
1
VOUT
VIN

Where C1 is the input capacitance value.
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic, tantalum, or low
ESR electrolytic capacitors are recommended.
Low ESR capacitors are preferred to keep the
output voltage ripple low. The output voltage
ripple can be estimated by:
VOUT
VOUT
fS L
1
VOUT
VIN
 RESR
8
1
fS
C2

Where C2 is the output capacitance value and
RESR is the equivalent series resistance (ESR)
value of the output capacitor.
In the case of ceramic capacitors, the
impedance at the switching frequency is
dominated by the capacitance. The output
voltage ripple is mainly caused by the
capacitance. For simplification, the output
voltage ripple can be estimated by:
ΔVOUT
8
VOUT
fS2 L
C2
1
VOUT
VIN

In the case of tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the
output ripple can be approximated to:
ΔVOUT
VOUT
fS L
1
VOUT
VIN
 RESR
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP1482 can be optimized for a wide range of
capacitance and ESR values.
Compensation Components
MP1482 employs current mode control for easy
compensation and fast transient response. The
system stability and transient response are
controlled through the COMP pin. COMP pin is
the output of the internal transconductance
error amplifier. A series capacitor-resistor
combination sets a pole-zero combination to
control the characteristics of the control system.
The DC gain of the voltage feedback loop is
given by:
A VDC
RLOAD GCS
A EA
VFB
VOUT
Where AVEA is the error amplifier voltage gain;
GCS is the current sense transconductance and
RLOAD is the load resistor value.
The system has two poles of importance. One
is due to the compensation capacitor (C3) and
the output resistor of the error amplifier, and the
other is due to the output capacitor and the load
resistor. These poles are located at:
fP1
GEA
2  C3 A VEA
fP2
1
2  C2 RLOAD
Where GEA is the error amplifier transconductance.
The system has one zero of importance, due to the
compensation capacitor (C3) and the compensation
resistor (R3). This zero is located at:
fZ1
1
2  C3 R3
The system may have another zero of
importance, if the output capacitor has a large
capacitance and/or a high ESR value. The zero,
due to the ESR and capacitance of the output
capacitor, is located at:
fESR
1
2  C2 RESR
MP1482 Rev. 1.31
www.MonolithicPower.com
8
7/9/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.

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