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RTL8201BL 데이터 시트보기 (PDF) - Realtek Semiconductor

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RTL8201BL Datasheet PDF : 29 Pages
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5:<7>
5:<6>
5:<5>
5:<4:0>
100BASE-TX
10FD
10Base-T
Selector
1 = 100Base-TX is supported by link partner
0 = 100Base-TX not supported by link partner
This bit will also be set after the link in 100Base is
established by parallel detection.
1 = 10Base-T full duplex is supported by link partner
0 = 10Base-T full duplex not supported by link partner
1 = 10Base-T is supported by link partner
0 = 10Base-T not supported by link partner
This bit will also be set after the link in 10Base is
established by parallel detection.
Link Partner’s binary encoded node selector
Currently only CSMA/CD <00001> is specified
RTL8201BL
1, RO
0, RO
0, RO
<00000>, RO
6.7 Register 6 Auto-negotiation Expansion Register(ANER)
This register contains additional status for NWay auto-negotiation.
Address
6:<15:5>
6:<4>
6:<3>
6:<2>
6:<1>
6:<0>
Name
Description/Usage
Reserved This bit is always set to 0.
MLF
Status indicating if a multiple link fault has occurred.
1 = fault occurred
0 = no fault occurred
LP_NP_ABLE Status indicating if the link partner supports Next
Page negotiation.
1 = supported
0 = not supported
NP_ABLE This bit indicates if the local node is able to send
additional Next Pages.
PAGE_RX This bit is set when a new Link Code Word Page has
been received. It is automatically cleared when the
auto-negotiation link partner’s ability register
(register 5) is read by management.
LP_NW_ABLE 1 = link partner supports Nway auto-negotiation.
Default/Attribute
0, RO
0, RO
0, RO
0, RO
0, RO
6.8 Register 16 Nway Setup Register(NSR)
Address
16:<15:12>
16:<11>
16:<10>
16:<9>
16:<8;3>
16:<2>
16:<1>
16:<0>
Name
Reserved
ENNWLE
Testfun
NWLPBK
Reserved
FLAGABD
FLAGPDF
FLAGLSC
Description/Usage
1 = LED4 Pin indicates linkpulse
1 = Auto-neg speeds up internal timer
1 = set Nway to loopback mode.
1 = Auto-neg experienced ability detect state
1 = Auto-neg experienced parallel detection fault state
1 = Auto-neg experienced link status check state
Default/Attribute
0, RW
0, RW
0, RW
0, RO
0, RO
0, RO
2002-03-29
11
Rev.1.2

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