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ADF7020BCP 데이터 시트보기 (PDF) - Analog Devices

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ADF7020BCP Datasheet PDF : 40 Pages
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Preliminary Technical Data
TIMING CHARACTERISTICS
VDD = 3 V ± 10%; VGND = 0 V, TA = 25°C, unless otherwise noted.
Guaranteed by design, but not production tested.
Table 2.
Parameter
Limit at TMIN to TMAX
Unit
t1
<10
ns
t2
<10
ns
t3
<25
ns
t4
<25
ns
t5
<10
ns
t6
<20
ns
t7
<TBD
ns
t8
<TBD
ns
t9
<TBD
ns
t10
<TBD
ns
Test Conditions/Comments
SDATA to SCLK Setup Time
SDATA to SCLK Hold Time
SCLK High Duration
SCLK Low Duration
SCLK to SLE Setup Time
SLE Pulse Width
SLE to SCLK Setup Time, Readback
SCLK to SREAD Data Valid, Readback
SREAD Hold Time after SCLK, Readback
SCLK to SLE Disable Time, Readback
ADF7020
SCLK
SDATA
DB31 (MSB)
t1
t2
DB30
t3
t4
DB2
DB1
(CONTROL BIT C2)
SLE
t1
t2
SCLK
Figure 2. Serial Interface Timing Diagram
SDATA
SLE
REG7 DB0
(CONTROL BIT C1)
t3
SREAD
t8
X
RV16
RV15
t9
Figure 3. Readback Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t6
t5
t10
RV2
RV1
Rev. PrH | Page 7 of 40

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