ADF7020BCP 데이터 시트보기 (PDF) - Analog Devices

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ADF7020BCP

High Performance ISM Band FSK/ASK Transceiver IC

Analog Devices 

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADF7020

VCOIN 1

VREG1 2

VDD1 3

RFOUT 4

RFGND 5

RFIN 6

RFINB 7

RLNA 8

VDD4 9

RSET 10

VREG4 11

GND4 12

PIN 1

INDICATOR

ADF7020

TOP VIEW

(Not to Scale)

36 CLKOUT

35 DATA CLK

34 DATA I/O

33 INT/LOCK

32 VDD2

31 VREG2

30 ADCIN

29 GND2

28 SCLK

27 SREAD

26 SDATA

25 SLE

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1

VCOIN

The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).

The higher the tuning voltage, the higher the output frequency.

2

VREG1

Regulator Voltage for PA Block. A 100 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

3

VDD1

Voltage Supply for PA Block. Decoupling capacitors (X7R or Tantalum) of 0.1 µF and 0.01 µF should be placed

as close as possible to this pin.

4

RFOUT

The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output

should be impedance matched to the desired load using suitable components. See the Transmitter section.

5

RFGND

Ground for Output Stage of Transmitter.

6

RFIN

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA

input to ensure maximum power transfer. See the LNA/PA Matching section.

7

RFINB

Complementary LNA Input. See the LNA/PA Matching section.

8

RLNA

External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

9

VDD4

Voltage supply for LNA/MIXER block. This pin should be decoupled to ground with a 0.01 µF capacitor.

10

RSET

External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance.

11

VREG4

Regulator Voltage for LNA/MIXER block. A 100 nF capacitor should be placed between this pin and GND for

regulator stability and noise rejection.

12

GND4

Ground for LNA/MIXER block.

13–18

MIX/FILT

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

19, 22

GND4

Ground for LNA/MIXER block.

20, 21, 23 FILT/TEST_A Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

24

CE

Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when CE

is low, and the part must be reprogrammed once CE is brought high.

25

SLE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the

four latches. A latch is selected using the control bits.

26

SDATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high

impedance CMOS input.

27

SREAD

Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The SCLK

input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.

28

SCLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

Rev. PrH | Page 9 of 40

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