STK22C48-N25 데이터 시트보기 (PDF) - Simtek Corporation
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STK22C48-N25 Datasheet PDF : 11 Pages
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STK22C48
DEVICE OPERATION
The STK22C48 has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static RAM. In nonvolatile mode, data is transferred
from SRAM to Nonvolatile Elements (the STORE
operation) or from Nonvolatile Elements to SRAM
(the RECALL operation). In this mode SRAM func-
tions are disabled.
NOISE CONSIDERATIONS
The STK22C48 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCAP and
VSS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK22C48 performs a READ cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A0-10 determines which of
the 2,048 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of tAVQV (READ cycle
#1). If the READ is initiated by E or G, the outputs will
be valid at tELQV or at tGLQV, whichever is later (READ
cycle #2). The data outputs will repeatedly respond
to address changes within the tAVQV access time with-
out the need for transitions on any control input pins,
and will remain valid until another address change or
until E or G is brought high, or W or HSB is brought
low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
POWER-UP RECALL
During power up, or after any low-power condition
(VCAP < VRESET), an internal RECALL request will be
latched. When VCAP once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK22C48 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
AutoStore™ OPERATION
The STK22C48 can be powered in one of three
modes.
During normal AutoStore™ operation, the
STK22C48 will draw current from VCCX to charge a
capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single
STORE operation. After power up, when the voltage
on the VCAP pin drops below VSWITCH, the part will
automatically disconnect the VCAP pin from VCCX and
initiate a STORE operation.
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68µF and
220µF (± 20%) rated at 6V should be provided.
In system power mode (Figure 3), both VCCX and
VCAP are connected to the + 5V power supply without
the 68µF capacitor. In this mode the AutoStore™
function of the STK22C48 will operate on the stored
system charge as power goes down. The user must,
however, guarantee that VCCX does not drop below
3.6V during the 10ms STORE cycle.
If an automatic STORE on power loss is not required,
then VCCX can be tied to ground and + 5V applied to
VCAP (Figure 4). This is the AutoStore™ Inhibit
mode, in which the AutoStore™ function is disabled.
If the STK22C48 is operated in this configuration,
references to VCCX should be changed to VCAP
throughout this data sheet. In this mode, STORE
operations may be triggered with the HSB pin. It is
not permissable to change between these three
options “on the fly”.
December 2002
7 Document Control # ML0004 rev 0.0
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