MPC973 데이터 시트보기 (PDF) - Motorola => Freescale

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MPC973

LOW VOLTAGE PLL CLOCK DRIVER

Motorola => Freescale 

exclusively to maintain the tight output–to–output skew of the

MPC973. The output waveform in Figure 15 shows a step in the

waveform, this step is caused by the impedance mismatch

seen looking into the driver. The parallel combination of the 43Ω

series resistor plus the output impedance does not match the

parallel combination of the line impedances. The voltage wave

launched down the two lines will equal:

VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40 V

At the load end the voltage will double, due to the near unity

reflection coefficient, to 2.8 V. It will then increment towards the

quiescent 3.0 V in steps separated by one round trip delay (in

this case 4.0 ns).

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 15 should be used. In this case the series terminating

resistors are reduced such that when the parallel combination

is added to the output buffer impedance the line impedance is

perfectly matched.

3.0

OutA

2.5

tD = 3.8956

2.0

In

1.5

OutB

tD = 3.9386

1.0

0.5

0

2

4

6

8

10 12 14

TIME (nS)

Figure 15. Single versus Dual Waveforms

MPC973

OUTPUT

BUFFER

7Ω

RS = 36 Ω ZO = 50 Ω

RS = 36 Ω ZO = 50 Ω

7 Ω + 36 Ω k 36 Ω = 50 Ω k 50 Ω

25 Ω = 25 Ω

Figure 16. Optimized Dual Line Termination

MPC973

SPICE level output buffer models are available for engineers

who want to simulate their specific interconnect schemes. In

addition IV characteristics are in the process of being

generated to support the other board level simulators in general

use.

Using the Output Freeze Circuitry

With the recent advent of a “green” classification for

computers the desire for unique power management among

system designers is keen. The individual output enable control

of the MPC973 allows designers, under software control, to

implement unique power management schemes into their

designs. Although useful, individual output control at the

expense of one pin per output is too high, therefore a simple

serial interface was derived to economize on the control pins.

The freeze control logic provides a mechanism through

which the MPC973 clock outputs may be frozen (stopped in the

logic ‘0’ state):

The freeze mechanism allows serial loading of the 12–bit

Serial Input Register, this register contains one program–

mable freeze enable bit for 12 of the 14 output clocks. The Qc0

and QFB outputs cannot be frozen with the serial port, this

avoids any potential lock up situation should an error occur in

the loading of the Serial Input Register. The user may program

an output clock to freeze by writing logic ‘0’ to the respective

freeze enable bit. Likewise, the user may programmably

unfreeze an output clock by writing logic ‘1’ to the respective

enable bit.

The freeze logic will never force a newly–frozen clock to a

logic ‘0’ state before the time at which it would normally

transition there. The logic simply keeps the frozen clock at logic

‘0’ once it is there. Likewise, the freeze logic will never force a

newly–unfrozen clock to a logic ‘1’ state before the time at which

it would normally transition there. The logic re–enables the

unfrozen clock during the time when the respective clock would

normally be in a logic ‘0’ state, eliminating the possibility of ‘runt’

clock pulses.

The user may write to the Serial Input register through the

Frz_Data input by supplying a logic ‘0’ start bit followed serially

by 12 NRZ freeze enable bits. The period of each Frz_Data bit

equals the period of the free–running Frz_Clk signal. The

Frz_Data serial transmission should be timed so the MPC973

can sample each Frz_Data bit with the rising edge of the

free–running Frz_Clk signal.

Start

Bit

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10 D11

D0-D3 are the control bits for Qa0-Qa3, respectively

D4-D7 are the control bits for Qb0-Qb3, respectively

D8-D10 are the control bits for Qc1-Qc3, respectively

D11 is the control bit for QSync

Figure 17. Freeze Data Input Protocol

MOTOROLA

11

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