MPC973 데이터 시트보기 (PDF) - Motorola => Freescale
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MPC973 Datasheet PDF : 16 Pages
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MPC973
`0'
fsela0
`0'
fsela1
`1'
fselb0
`1'
fselb1
`0'
fselc0
`1'
fselc1
`0'
fselFB0
4
Qa
4
Qb
4
Qc
100 MHz
40 MHz
66.66 MHz
`1'
fselFB1
`0'
fselFB2
QFB
50 MHz
50MHz
Input Ref
Ext_FB
VCO = 400MHz
Figure 8. Programming Configuration Example
MPC973
MPC973
`0'
fsela0
`0'
fsela1
`0'
fselb0
`0'
fselb1
`1'
fselc0
`1'
fselc1
`1'
fselFB0
4
Qa
4
Qb
4
Qc
60 MHz (Processor)
60 MHz (Processor)
30 MHz (PCI)
`1'
fselFB1
`0'
fselFB2
QFB
24 MHz (Floppy Disk Clk)
24MHz
Input Ref
Ext_FB
Figure 9. Generating Pentium Clocks from Floppy Clock
MPC973
`1'
fsela0
`1'
fsela1
`0'
fselb0
`1'
fselb1
`1'
fselc0
`1'
fselc1
`1'
fselFB0
4
Qa
4
Qb
4
Qc
33 MHz (PCI)
50 MHz (Processor)
50 MHz (Processor)
`1'
fselFB1
`1'
fselFB2
QFB
20 MHz (Ethernet)
20MHz
Input Ref
Ext_FB
Figure 10. Generating MPC604 Clocks from Ethernet Clocks
MPC973
`0'
fsela0
`0'
fsela1
`0'
fselb0
`0'
fselb1
`1'
fselc0
`0'
fselc1
`0'
fselFB0
`0'
fselFB1
`0'
fselFB2
4
Qa
4
Qb
2
Qc
2
Qc
`1'
Inv_Clk
QFB
66MHz
Input Ref
Ext_FB
`0'
66 MHz `1'
`0'
66 MHz `1'
`1'
66 MHz `1'
`0'
66 MHz `0'
`0'
`0'
fsela0
fsela1
fselb0
fselb1
fselc0
fselc1
fselFB0
fselFB1
fselFB2
Inv_Clk
MPC973
Input Ref
Ext_FB
4
Qa
4
Qb
4
Qc
QFB
33 MHz Shifted 90°
33 MHz Shifted 90°
33 MHz Shifted 90°
66 MHz
66 MHz
66 MHz
33 MHz
Shifted 90°
Figure 11. Phase Delay Using Multiple MPC973’s
Recommended External Reset Timing
For MPC973 applications requiring synchronization of the
output clock to the input clock and if fselFB2 = 1, the assertion
of the MR is recommended. The timing of asserting MR should
be as shown in Figure 12. The power supply should be at or
above the minimum specified voltage and the reference clock
input (refclk) should be present a minimum of t1 prior to the
reset pulse being applied to the MR pin.
MOTOROLA
9
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