ACS103 데이터 시트보기 (PDF) - Unspecified
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ACS103 Datasheet PDF : 10 Pages
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The power coupled to the cable is a function of the recommended choice since it is further away from
efficiency of the LED, the current applied to the LED the sensitive analogue pins. However, pin 41 is
and the diameter of the fiber optic cable. The larger available for designers if required.
the cable diameter the greater the power coupled.
The conversion current produced by the receive Digital Mode
diode is a function of the LED efficiency and the
cable diameter. The conversion efficiency is
measured in terms of its ability to convert the
available power to current, known as the
responsivity, given by (A/W). Some examples of link
The ACS103 may be used as a controller and data
buffer which allows the device to be used with an
external amplifier and receiver, e.g. for non-fiber
applications. Check with Acapella for details.
budgets are given in the Table 1., though note that Data delay and skew
significantly better "A" spec. LEDs available, e.g.
from Acapella. “A” spec. LEDs can offer > 12 dB link The data delay in synchronous mode is typically 48
budget on 50 µm fiber.
data-bit periods and worst case 100 data-bit periods.
When configured in asynchronous mode the worst
Maximum Link Length
case data delay is 300 µs at 9.216 MHz and 550 µs at
2
5 MHz. The additional data transmission channels
The internal timing chain within the ACS103 limits (XI1/2/3) are delayed by up to 1.2 ms in 'Standard'
the link length to 2.5 km ('Standard' mode) and 5 km mode and up to 2.4 ms in 'Double' mode when used
('Double' mode) with a crystal frequency of with a crystal frequency of 9.216 MHz. For other
9.216 MHz. However, the maximum link length as crystal values the delay changes inversely
determined by the ACS103 timing chain is inversely proportional to the frequency of operation.
proportional to the crystal frequency. Please contact
Acapella if you wish to discuss longer links.
The worst case data skews between the main data
channels TxD1/RxD1, TxD2/RxD2 and TxD3/RxD3
TxD inputs
across the link are as follows.
There is a choice of pins for TxD1, pins 12 and 41.
Only one input should be used. The other input will
pull-up to VDD via an internal resistor. Pin 12 is the
Synchronous : zero data bits.
Asynchronous : 216 * (crystal clock period).
1 DR3
2 DR1
3 IC
4 DM1
5 RxD1
6 IC
7 XO3
8 IC
9 NC
10 RTS / XI1
11 TxD3
12 TxD1
13 VD+
14 XTI
15 XTO
16 CKC
17 TxCL
18 RxCL
19 XI3
20 DM2
21 SEL
22 DM3
23 GND
24 DTR / XI2
25 TxD2
26 ERD
27 NC
28 IC
29 RxD2
30 PORB
31 RxD3
32 CTS / XO1
33 DSR / XO2
34 DCDB
ACS103 Issue 2.03 May 1996.
10
60
11
59
12
58
13
57
14
56
15
55
16
17
ACAPELLA
54
53
18
52
19
ACS103
51
20
50
21
1-Fiber Modem
49
22
48
23
47
24
46
25
45
26
44
Figure 1. Top view of 68 PLCC package
NC = Not Connected IC = Internally Connected
6
VD+ 68
VD+ 67
GND 66
GND 65
DR2 64
TRC 63
DR4 62
NC 61
NC 60
NC 59
NC 58
NC 57
VG 56
VA+ 55
CON2 54
LDP 53
NC 52
NC 51
LDN 50
CON1 49
CNT 48
GND 47
NC 46
NC 45
NC 44
NC 43
IC 42
TXD1 41
LIN 40
RSS 39
VD+ 38
VD+ 37
GND 36
GND 35
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