UJA1075A 데이터 시트보기 (PDF) - NXP Semiconductors.
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UJA1075A Datasheet PDF : 54 Pages
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NXP Semiconductors
UJA1075A
High-speed CAN/LIN core system basis chip
Table 2. Pin description …continued
Symbol
Pin
Description
WAKE1
18
local wake-up input 1
WAKE2
19
local wake-up input 2
V2
20
5 V voltage regulator output for CAN
CANH
21
CANH bus line
CANL
22
CANL bus line
GND
23
ground
SPLIT
24
CAN bus common mode stabilization output
LIN
25
LIN bus line
DLIN
26
LIN termination resistor connection
i.c.
27
internally connected; should be left floating
WBIAS
28
control pin for external wake biasing transistor
VEXCC
29
current measurement for external PNP transistor; this pin is connected to
the collector of the external PNP transistor
TEST2
30
test pin; pin should be connected to ground
VEXCTRL 31
control pin of the external PNP transistor; this pin is connected to the base
of the external PNP transistor
BAT
32
battery supply for the SBC
The exposed die pad at the bottom of the package allows for better heat dissipation from
the SBC via the printed-circuit board. The exposed die pad is not connected to any active
part of the IC and can be left floating, or can be connected to GND.
6. Functional description
The UJA1075A combines the functionality of a high-speed CAN transceiver, a LIN
transceiver, two voltage regulators and a watchdog (UJA1075A/xx/WD versions) in a
single, dedicated chip. It handles the power-up and power-down functionality of the ECU
and ensures advanced system reliability. The SBC offers wake-up by bus activity, by
cyclic wake-up and by the activation of external switches. Additionally, it provides a
periodic control signal for pulsed testing of wake-up switches, allowing low-current
operation even when the wake-up switches are closed in Standby mode.
All transceivers are optimized to be highly flexible with regard to bus topologies. In
particular, the high-speed CAN transceiver is optimized to reduce ringing (bus reflections).
V1, the main voltage regulator, is designed to power the ECU's microcontroller, its
peripherals and additional external transceivers. An external PNP transistor can be added
to improve heat distribution. V2 supplies the integrated high-speed CAN transceiver. The
watchdog is clocked directly by the on-chip oscillator and can be operated in Window,
Timeout and Off modes.
UJA1075A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 28 January 2011
© NXP B.V. 2011. All rights reserved.
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