HT82K68A-28 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT82K68A-28

Multimedia Keyboard Encoder 8-Bit Mask MCU

Holtek Semiconductor 

HT82K68A

other circuits to remain in their original state. Some reg-

isters remain unchanged during other reset conditions.

Most registers are reset to the ²initial condition² when

the reset conditions are met. By examining the PDF and

TO flags, the program can distinguish between different

²chip resets².

TO PDF

RESET Conditions

0 0 RESET reset during power-up

u u RESET reset during normal operation

0 1 RESET wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² means ²unchanged²

VDD

RESET

S S T T im e - o u t

C h ip R e s e t

tS S T

Reset Timing Chart

V DD

RESET

Reset Circuit

H A LT

W DT

RESET

W DT

T im e - o u t

R eset

O SC1

SST

1 0 -s ta g e

R ip p le C o u n te r

W a rm R e s e t

C o ld

R eset

P o w e r - o n D e te c tio n

Reset Configuration

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem powers up or when it awakes from the HALT state.

When a system power-up occurs, the SST delay is

added during the reset period. But when the reset co-

mes from the RESET pin, the SST delay is disabled.

Any wake-up from HALT will enable the SST delay.

The functional unit chip reset status is shown below.

Program Counter

000H

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer Counter

Off

Input/Output Ports Input mode

Stack Pointer

Points to the top of the stack

Timer Counter

A timer counter (TMR) is implemented in the

HT82K68A. The timer counter contains an 8-bit pro-

grammable count-up counter and the clock may come

from the system clock divided by 4.

Using the internal instruction clock, there is only one ref-

erence time-base.

There are two registers related to the timer counter;

TMR ([0DH]), TMRC ([0EH]). Two physical registers are

mapped to TMR location; writing TMR makes the start-

ing value be placed in the timer counter preload register

and reading TMR gets the contents of the timer counter.

The TMRC is a timer counter control register, which de-

fines some options.

In the timer mode, once the timer counter starts count-

ing, it will count from the current contents in the timer

counter to FFH. Once overflow occurs, the counter is re-

loaded from the timer counter preload register and gen-

erates the interrupt request flag (TF; bit 5 of INTC) at the

same time.

Label

¾

TON

TM0

TM1

Bits

0~3, 5

4

6

7

Function

Unused bit, read as "0"

To enable/disable timer counting (0= disabled; 1= enabled)

10= Timer mode (internal clock)

TMRC (0EH) Register

Rev. 1.70

12

December 26, 2005

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