QL6250-E 데이터 시트보기 (PDF) - QuickLogic Corporation

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QL6250-E

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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tRCRD

RCLK to RD: time between the active READ CLOCK edge and the time when the

data is available at RD

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rPDRD

RA to RD: time between when the READ ADDRESS is input and when the DATA

is output

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4.38 ns

-

2.06 ns

RCLK

RA

tSRA

tHRA

RE

tSRE

tHRE

RD

old data

new data

rPDRD

tRCRD

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