CXD2728Q 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD2728Q Datasheet PDF : 61 Pages
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CXD2728Q
Microcomputer Interface Timing
Transfer timing for address section, transfer mode section and data section LSB
RVDT
SCK
Address LSB
tSWL tSWH
XLAT
REDY
Mode MSB
tDS tDH
2.0V
0.8V
2.0V
0.8V
tSLP
tLWL
Data LSB
tLSD
2.0V
0.8V
Data MSB
Transfer timing from data section MSB to address section and transfer mode section
RVDT Data MSB
SCK
XLAT
REDY
tSS
tSBD
Address LSB
tSLD
tBSP
tLDR
Mode MSB
2.0V
0.8V
tRLP
2.0V
0.8V
2.0V
0.8V
Item
RVDT data setup time relative to SCK rise
RVDT data hold time from SCK rise
SCK Low level width
SCK High level width
XLAT Low level width
XLAT High level width
SCK rise preceding time relative to XLAT rise
SCK rise wait time relative to XLAT rise
Delay time to REDY fall relative to SCK rise
REDY fall preceding time relative to SCK rise
REDY rise preceding time relative to XLAT rise
REDY rise preceding time relative to SCK fall
XLAT fall wait time relative to SCK rise
XLAT fall delay time relative to REDY fall
SCK rise wait time for next transfer
Symbol Min.
Max. Unit
tDS
20
ns
tDH 1t + 20
ns
tSWL 1t + 20
ns
tSWH 1t + 20
ns
tLWL 1t + 20
ns
tLWH 1t + 20
ns
tSLP
20
ns
tLSD 3t + 20
ns
tSBD
4t + 50 ns
tBSP
20
ns
tRLP
20
ns
tRSDP
20
ns
tSLD 3t + 20
ns
tLDR
20
ns
tSS 2t + 40
ns
Notes) 1. t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs)
2. The REDY pin is the value for CL = 60pF.
–7–
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