CXA2050 데이터 시트보기 (PDF) - Sony Semiconductor

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CXA2050

Y/C/RGB/D for PAL/NTSC Color TVs

Sony Semiconductor 

Pin

No.

Symbol

52 VSIN

CXA2050S

Equivalent circuit

Description

15k

Sync signal input for V sync separation.

147

52

Input a 2Vp-p Y signal (or a 0.6Vp-p

4.1V sync signal).

20µA

53 HSIN

54 SYNCOUT

55 VM

56 SCL

14k

Sync signal input for H sync separation.

147

53

Input a 2Vp-p Y signal (or a 0.6Vp-p sync

3.2V signal).

10µA

Sync signal output for VSIN and HSIN.

1.2k

The output can be selected from the

internal sync signals (Pin 60 or Pin 62) or

147

54

40k

the external sync signal (Pin 63) by the

I2C bus.

Output signal level: 2Vp-p

240µA

(0.6Vp-p sync only)

Input/output gain: 6dB

Outputs the differential waveform of the

VM (Velocity Modulation) Y signal.

500

The signal advanced for 200ns from

1.2k

YOUT is output. The delay time versus

147

55

YIN is determined by the DL setting of

30k the I2C bus. This output level can be set

at 2.65Vp-p or 1.1Vp-p by the I2C bus.

400µA

Pedestal level is DC6.2V.

This output can also be turned off by

YS1, YM, and YS2.

4k

56

I2C bus protocol SCL (Serial Clock) input.

VILMAX = 1.5V

VIHMIN = 3.5V

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