M38031F3L-XXXSP 데이터 시트보기 (PDF) - Renesas Electronics

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M38031F3L-XXXSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Renesas Electronics 

3803 Group (Spec.L)

On-going Routine

Interrupt request(1)

Push Return

Address

on Stack

M(S)←(PCH)

(S)←(S) − 1

M(S)←(PCL)

(S)←(S) − 1

Subroutine

Execute RTS

POP Return

Address from

Stack

(S)←(S) + 1

(PCL)←M(S)

(S)←(S) + 1

(PCH)←M(S)

Execute JSR

M(S)←(PCH)

(S)←(S) − 1

Push Return Address

on Stack

M(S)←(PCL)

(S)←(S) − 1

M(S)←(PS)

Push Contents of

Processor

Status Register on Stack

(S)←(S) − 1

Interrupt

Service Routine

Execute RTI

I Flag is Set from

“0” to “1”

Fetch the Jump

Vector

(S)←(S) + 1

(PS)←M(S)

POP Contents of

Processor Status Register

from Stack

(S)←(S) + 1

(PCL)←M(S)

(S)←(S) + 1

POP Return

Address from Stack

(PCH)←M(S)

Note 1 : Condition for acceptance of an interrupt → Interrupt enable flag is “1”

Interrupt disable flag is “0”

Fig 8. Register push and pop at interrupt generation and subroutine call

Table 4 Push and pop instructions of accumulator or processor status register

Accumulator

Processor status register

Push instruction to stack

PHA

PHP

Pop instruction from stack

PLA

PLP

Rev.1.00 Apr 2, 2007 Page 10 of 117

REJ03B0212-0100

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